公开(公告)号：US08887106B2

公开(公告)日：2014-11-11

申请号：US13370994

申请日：2012-02-10

申请人： Chia-Ming Ho ,  Ke-Ying Su ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

发明人： Chia-Ming Ho ,  Ke-Ying Su ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70441 ,  G06F17/5072

摘要： A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule.

摘要翻译： 产生导电特征的偏置调节布局设计的方法包括接收导电特征的布局设计。 如果布局设计的几何配置在预定标准的第一组内，则根据第一布局偏置规则产生导电特征的偏置调整布局设计。 如果布局设计的几何结构在预定标准的第二组内，则根据第二布局偏差规则产生导电特征的偏置调节布局设计。

公开(公告)号：US08856696B2

公开(公告)日：2014-10-07

申请号：US13354707

申请日：2012-01-20

申请人： Wen-Hao Chen ,  Yuan-Te Hou ,  Yi-Kan Cheng

发明人： Wen-Hao Chen ,  Yuan-Te Hou ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5077

摘要： Methods are disclosed of modifying an integrated circuit (IC) design that utilizes multiple patterning technology (MPT). The methods include configuring a first layout of an integrated circuit, having at least one layer with features to be formed utilizing fabrication by at least two masks. The at least one layer includes a plurality of active cells and a plurality of spare cells. A second layout is configured to re-route the spare cells and active cells, wherein the re-routing utilizes at least a portion of the plurality of spare cells. Fewer than all of the at least two masks are replaced to configure the second layout.

摘要翻译： 公开了改进利用多重图案化技术（MPT）的集成电路（IC）设计的方法。 所述方法包括配置集成电路的第一布局，其具有至少一层具有通过至少两个掩模的制造而形成的特征的层。 该至少一层包括多个活动单元和多个备用单元。 第二布局被配置为重新路由备用单元和活动单元，其中重新路由使用多个备用单元的至少一部分。 比所有至少两个掩模更少，以配置第二个布局。

公开(公告)号：US08601408B2

公开(公告)日：2013-12-03

申请号：US13269757

申请日：2011-10-10

申请人： Huang-Yu Chen ,  Yuan-Te Hou ,  Chung-Min Fu ,  Chung-Hsing Wang ,  Wen-Hao Chen ,  Yi-Kan Cheng

发明人： Huang-Yu Chen ,  Yuan-Te Hou ,  Chung-Min Fu ,  Chung-Hsing Wang ,  Wen-Hao Chen ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

公开(公告)号：US20130290916A1

公开(公告)日：2013-10-31

申请号：US13459288

申请日：2012-04-30

申请人： Hui Yu LEE ,  Feng Wei KUO ,  Ching-Shun YANG ,  Yi-Kan CHENG ,  Jui-Feng KUAN

发明人： Hui Yu LEE ,  Feng Wei KUO ,  Ching-Shun YANG ,  Yi-Kan CHENG ,  Jui-Feng KUAN

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5081

摘要： A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.

摘要翻译： 一种方法包括从半导体电路的第一布局提取第一网表并基于第一网表估计与布局有关的效果数据。 基于使用电子设计自动化工具的第一网表执行半导体电路的第一仿真，并且基于使用电子设计自动化工具的电路示意图来执行半导体电路的第二仿真。 计算至少一个与布局相关的效果的重量和灵敏度，并且基于重量和灵敏度来调整半导体电路的第一布局以提供半导体电路的第二布局。 第二布局存储在非瞬态存储介质中。

公开(公告)号：US20130227501A1

公开(公告)日：2013-08-29

申请号：US13406108

申请日：2012-02-27

申请人： Ching-Shun YANG ,  Ze-Ming WU ,  Hsiao-Shu CHAO ,  Yi-Kan CHENG

发明人： Ching-Shun YANG ,  Ze-Ming WU ,  Hsiao-Shu CHAO ,  Yi-Kan CHENG

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5081 ,  G03F7/00 ,  G06F17/5036 ,  G06F2217/82

摘要： In a semiconductor device design method performed by at least one processor, first and second electrical components are extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second electrical components in the semiconductor substrate. Parasitic parameters of a coupling in the semiconductor substrate between the first and second electrical components are extracted using a first tool. Intrinsic parameters of the first and second electrical components are extracted using a second tool different from the first tool. The extracted parasitic parameters and intrinsic parameters are combined into a model of the semiconductor device. The parasitic parameters of the coupling are extracted based on a model of the coupling included in the second tool.

摘要翻译： 在由至少一个处理器执行的半导体器件设计方法中，从半导体器件的布局中提取第一和第二电子部件。 半导体器件具有半导体衬底和半导体衬底中的第一和第二电子部件。 使用第一工具提取第一和第二电气部件之间的半导体衬底中的耦合的寄生参数。 使用与第一工具不同的第二工具提取第一和第二电气部件的固有参数。 提取的寄生参数和固有参数被组合成半导体器件的模型。 基于包括在第二工具中的耦合模型，提取耦合的寄生参数。

公开(公告)号：US20130205266A1

公开(公告)日：2013-08-08

申请号：US13365546

申请日：2012-02-03

申请人： Wen-Hao Chen ,  Yuan-Te Hou ,  Yi-Kan Cheng

发明人： Wen-Hao Chen ,  Yuan-Te Hou ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/62

摘要： A method comprises: accessing a persistent, machine readable storage medium containing data representing an integrated circuit (IC) design to be fabricated using multi-patterning; identifying at least one network of conductive patterns configured to transmit signals that substantially impact timing of at least one circuit in the IC; pre-grouping the at least one network of conductive patterns in a first group; and electronically providing data to an electronic design automation (EDA) tool to cause inclusion in a first single photomask of all portions of the patterns within the first group that are to be formed in a single layer of the IC, wherein the single layer is to be multi-patterned using at least two photomasks.

摘要翻译： 一种方法包括：访问包含表示将使用多图案化制造的集成电路（IC）设计的数据的持久的机器可读存储介质; 识别被配置为传输基本上影响所述IC中的至少一个电路的定时的信号的导电图案的至少一个网络; 将第一组中的至少一个导电图案网络预分组; 以及将电子数据提供给电子设计自动化（EDA）工具，以使所述第一组中将被形成在所述IC的单个层中的所述图案的所有部分的第一单个光掩模包括在其中，所述单层为 使用至少两个光掩模进行多图案化。

公开(公告)号：US08434043B1

公开(公告)日：2013-04-30

申请号：US13480847

申请日：2012-05-25

申请人： Chin-Chang Hsu ,  HungLung Lin ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

发明人： Chin-Chang Hsu ,  HungLung Lin ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： The present disclosure relates to a method and apparatus for identifying pre-coloring violations and for providing hints and/or warnings to a designer to eliminate the pre-coloring violations. In some embodiments, the method is performed by identifying G0-spaces within a double patterning technology (DPT) layer, of an integrated chip (IC) layout, having a plurality of pre-colored shapes. Violation paths extending between the pre-colored shapes are identified based upon the G0-spaces. Good paths (i.e., paths that will not cause a violation) and bad paths (i.e., paths that will cause a violation) between the pre-colored shapes are also identified. Hints and/or warnings are generated based upon the identified good and bad paths, wherein the hints and/or warnings provide guidance to eliminate the violation paths and develop a violation free IC layout.

摘要翻译： 本公开涉及一种用于识别预着色违规的方法和装置，并且用于向设计者提供提示和/或警告以消除预着色违规。 在一些实施例中，该方法通过识别具有多个预着色形状的集成芯片（IC）布局的双图案形成技术（DPT）层内的G0空间来执行。 基于G0空格识别在预色图案之间延伸的违规路径。 还识别出良好路径（即，不会引起违规的路径）和不良路径（即将导致违规的路径）。 提示和/或警告是基于所识别的好路径和不良路径生成的，其中提示和/或警告提供指导以消除违规路径并开发无违规IC布局。

公开(公告)号：US08418098B2

公开(公告)日：2013-04-09

申请号：US12054195

申请日：2008-03-24

申请人： Chi-Heng Huang ,  Gary Lin ,  Chu-Fu Chen ,  Yi-Kan Cheng ,  Fu-Lung Hsueh

发明人： Chi-Heng Huang ,  Gary Lin ,  Chu-Fu Chen ,  Yi-Kan Cheng ,  Fu-Lung Hsueh

IPC分类号： G06F17/50 ,  H03K5/22

CPC分类号： G06F17/5036 ,  G06F17/5009

摘要： A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits.

摘要翻译： 提供了用于验证集成电路设计的验证系统。 验证系统包括：功能块查找模块，被配置为识别集成电路设计中的潜在敏感电路; 和搜索模块。 搜索模块被配置为从潜在敏感电路中找到敏感电路; 并验证敏感电路。

公开(公告)号：US08255837B2

公开(公告)日：2012-08-28

申请号：US12616970

申请日：2009-11-12

申请人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Yuan-Te Hou ,  Yung-Chin Hou ,  Li-Chun Tien

发明人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Yuan-Te Hou ,  Yung-Chin Hou ,  Li-Chun Tien

IPC分类号： G06F17/50

CPC分类号： G03F1/70 ,  G03F1/00

摘要： A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.

摘要翻译： 设计用于芯片布局的双重图案掩模组的方法包括设计标准单元。 在每个标准单元中，所有左边界图案被分配有第一指示符和第二指示符中的一个，并且所有右边图案都被分配有第一指示符和第二指示符中的另外一个。 该方法还包括将标准单元放置在芯片布局的一行中。 从行中的一个标准单元开始，标记单元的指示符更改在整行中传播。 具有第一指示符的标准单元中的所有图案被转移到双图案掩模组的第一掩模。 具有第二指示器的标准单元中的所有图案被转移到双重图案掩模组的第二掩模。

公开(公告)号：US08239806B2

公开(公告)日：2012-08-07

申请号：US12649979

申请日：2009-12-30

申请人： Huang-Yu Chen ,  Yuan-Te Hou ,  Gwan Sin Chang ,  Wen-Ju Yang ,  Zhe-Wei Jiang ,  Yi-Kan Cheng ,  Lee-Chung Lu

发明人： Huang-Yu Chen ,  Yuan-Te Hou ,  Gwan Sin Chang ,  Wen-Ju Yang ,  Zhe-Wei Jiang ,  Yi-Kan Cheng ,  Lee-Chung Lu

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.

摘要翻译： 一种方法包括接收要包括在IC布局中的多个电路部件的标识。 生成表示连接两个电路部件的第一图案的数据。 第一图案具有多个片段。 至少两个片段具有彼此垂直的纵向方向。 保留与至少两个段中的至少一个相邻的至少一个无图案区域。 生成表示在第一图案附近的一个或多个附加图案的数据。 在无模式区域中没有形成附加图案。 第一种图案和附加图案形成双重图案化顺应的图案集合。 将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。