公开(公告)号：US20080176365A1

公开(公告)日：2008-07-24

申请号：US12077973

申请日：2008-03-24

申请人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

发明人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

摘要： A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.

摘要翻译： 提供了一种制造门控半导体器件的方法。 这种方法可以包括图案化衬底的单晶半导体区域，以在与衬底的主表面平行的横向方向上延伸并且沿至少基本上垂直且至少基本垂直于主表面的方向延伸，半导体 区域具有第一侧和第二侧，例如远离第一侧。 第一栅极可以形成在第一侧上，第一栅极在横向上具有第一栅极长度。 第二栅极可以形成在第二侧上，第二栅极在横向上具有与第一栅极长度不同的第二栅极长度。 在一个实施例中，第二栅极长度可以比​​第一栅极长度短。 在一个实施例中，第一栅极可以主要由多晶硅锗组成，第二栅极可以由多晶硅组成。

公开(公告)号：US07087952B2

公开(公告)日：2006-08-08

申请号：US10978951

申请日：2004-11-01

申请人： Huilong Zhu ,  Bruce B. Doris ,  Jochen Beintner

发明人： Huilong Zhu ,  Bruce B. Doris ,  Jochen Beintner

IPC分类号： H01L29/788

CPC分类号： H01L29/78684 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7881

摘要： A non-volatile storage cell in a Fin Field Effect Transistor (FinFET) and a method of forming an Integrated Circuit (IC) chip including the non-volatile storage cell. Each FET includes a control gate along one side of a semiconductor (e.g., silicon) fin, a floating gate along an opposite of the fin and a program gate alongside the floating gate. Control gate device thresholds are adjusted by adjusting charge on the floating gate.

摘要翻译： Fin场效应晶体管（FinFET）中的非易失性存储单元以及形成包括非易失性存储单元的集成电路（IC）芯片的方法。 每个FET包括沿着半导体（例如硅）翅片的一侧的控制栅极，沿着鳍片的相对的浮动栅极和沿着浮动栅极的编程栅极。 通过调节浮动栅极上的电荷来调节控制栅极器件的阈值。

公开(公告)号：US07785944B2

公开(公告)日：2010-08-31

申请号：US12077973

申请日：2008-03-24

申请人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

发明人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

IPC分类号： H01L21/84

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

摘要： A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.

摘要翻译： 提供了一种制造门控半导体器件的方法。 这种方法可以包括图案化衬底的单晶半导体区域，以在与衬底的主表面平行的横向方向上延伸并且沿至少基本上垂直且至少基本垂直于主表面的方向延伸，半导体 区域具有第一侧和第二侧，例如远离第一侧。 第一栅极可以形成在第一侧上，第一栅极在横向上具有第一栅极长度。 第二栅极可以形成在第二侧上，第二栅极在横向上具有与第一栅极长度不同的第二栅极长度。 在一个实施例中，第二栅极长度可以比​​第一栅极长度短。 在一个实施例中，第一栅极可以主要由多晶硅锗组成，第二栅极可以由多晶硅组成。

公开(公告)号：US07348641B2

公开(公告)日：2008-03-25

申请号：US10711182

申请日：2004-08-31

申请人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

发明人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

IPC分类号： H01L29/94

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

摘要： A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.

摘要翻译： 提供了门控半导体器件，其中主体具有在平行于衬底的主表面的横向方向上延伸的第一尺寸，以及在至少基本上垂直且至少基本垂直于主表面的方向上延伸的第二尺寸， 所述主体具有与所述第一侧相对的第一侧和第二侧。 门控半导体器件包括覆盖第一侧的第一栅极，并且在横向上具有第一栅极长度。 门控半导体器件还包括覆盖第二侧的第二栅极，第二栅极在横向上具有不同于第一栅极长度的第二栅极长度，并且优选地短于第一栅极长度。 在一个实施例中，第一栅极和第二栅极彼此电隔离。 在另一个实施例中，第一栅极主要由多晶硅锗组成，第二栅极主要由多晶硅组成。

公开(公告)号：US07091566B2

公开(公告)日：2006-08-15

申请号：US10717737

申请日：2003-11-20

申请人： Huilong Zhu ,  Jochen Beintner ,  Bruce B. Doris ,  Ying Zhang

发明人： Huilong Zhu ,  Jochen Beintner ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7856

摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.

摘要翻译： 包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 每个FET包括沿半导体（例如，硅）翅片的一侧的器件栅极和沿鳍片相对的背偏置栅极。 背偏置栅极电介质的不同之处在于器件栅极电介质的材料和/或厚度。 可以通过调整背偏置栅极电压来调整器件阈值。

公开(公告)号：US20050110085A1

公开(公告)日：2005-05-26

申请号：US10717737

申请日：2003-11-20

申请人： Huilong Zhu ,  Jochen Beintner ,  Bruce Doris ,  Ying Zhang

发明人： Huilong Zhu ,  Jochen Beintner ,  Bruce Doris ,  Ying Zhang

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7856

摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.

摘要翻译： 包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 每个FET包括沿半导体（例如，硅）翅片的一侧的器件栅极和沿鳍片相对的背偏置栅极。 背偏置栅极电介质的不同之处在于器件栅极电介质的材料和/或厚度。 可以通过调整背偏置栅极电压来调整器件阈值。

公开(公告)号：US20070181930A1

公开(公告)日：2007-08-09

申请号：US10711182

申请日：2004-08-31

申请人： Huilong Zhu ,  Bruce Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip Oldiges

发明人： Huilong Zhu ,  Bruce Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip Oldiges

IPC分类号： H01L27/108

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

摘要： A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.

摘要翻译： 提供了门控半导体器件，其中主体具有在平行于衬底的主表面的横向方向上延伸的第一尺寸，以及在至少基本上垂直且至少基本垂直于主表面的方向上延伸的第二尺寸， 所述主体具有与所述第一侧相对的第一侧和第二侧。 门控半导体器件包括覆盖第一侧的第一栅极，并且在横向上具有第一栅极长度。 门控半导体器件还包括覆盖第二侧的第二栅极，第二栅极在横向上具有不同于第一栅极长度的第二栅极长度，并且优选地短于第一栅极长度。 在一个实施例中，第一栅极和第二栅极彼此电隔离。 在另一个实施例中，第一栅极主要由多晶硅锗组成，第二栅极主要由多晶硅组成。

公开(公告)号：US20060091450A1

公开(公告)日：2006-05-04

申请号：US10978951

申请日：2004-11-01

申请人： Huilong Zhu ,  Bruce Doris ,  Jochen Beintner

发明人： Huilong Zhu ,  Bruce Doris ,  Jochen Beintner

IPC分类号： H01L29/788 ,  H01L29/76

CPC分类号： H01L29/78684 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7881

摘要： A non-volatile storage cell in a Fin Field Effect Transistor (FinFET) and a method of forming an Integrated Circuit (IC) chip including the non-volatile storage cell. Each FET includes a control gate along one side of a semiconductor (e.g., silicon) fin, a floating gate along an opposite of the fin and a program gate alongside the floating gate. Control gate device thresholds are adjusted by adjusting charge on the floating gate.

公开(公告)号：US08497168B2

公开(公告)日：2013-07-30

申请号：US13071940

申请日：2011-03-25

申请人： Bruce B. Doris ,  Haining Yang ,  Huilong Zhu

发明人： Bruce B. Doris ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/335 ,  H01L21/8232

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/7843

摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

摘要翻译： 在制造互补的金属氧化物半导体（CMOS）场效应晶体管（包括nMOS和pMOS晶体管）的情况下，通过使用在nMOS或pMOS晶体管（或两者）上分层各种应力薄膜来增强或调节载流子迁移率， 取决于层的性质并且将应力层彼此隔离并且在所选位置具有附加层的其它结构。 因此，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

公开(公告)号：US08008724B2

公开(公告)日：2011-08-30

申请号：US10695748

申请日：2003-10-30

申请人： Bruce B. Doris ,  Haining Yang ,  Huilong Zhu

发明人： Bruce B. Doris ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L23/62

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/7843

摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

摘要翻译： 在制造互补的金属氧化物半导体（CMOS）场效应晶体管（包括nMOS和pMOS晶体管）的情况下，通过使用在nMOS或pMOS晶体管（或两者）上分层各种应力薄膜来增强或调节载流子迁移率， 取决于层的性质并且将应力层彼此隔离并且在所选位置具有附加层的其它结构。 因此，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。