公开(公告)号：US20050110085A1

公开(公告)日：2005-05-26

申请号：US10717737

申请日：2003-11-20

申请人： Huilong Zhu ,  Jochen Beintner ,  Bruce Doris ,  Ying Zhang

发明人： Huilong Zhu ,  Jochen Beintner ,  Bruce Doris ,  Ying Zhang

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7856

摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.

摘要翻译： 包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 每个FET包括沿半导体（例如，硅）翅片的一侧的器件栅极和沿鳍片相对的背偏置栅极。 背偏置栅极电介质的不同之处在于器件栅极电介质的材料和/或厚度。 可以通过调整背偏置栅极电压来调整器件阈值。

公开(公告)号：US20070181930A1

公开(公告)日：2007-08-09

申请号：US10711182

申请日：2004-08-31

申请人： Huilong Zhu ,  Bruce Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip Oldiges

发明人： Huilong Zhu ,  Bruce Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip Oldiges

IPC分类号： H01L27/108

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

摘要： A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.

摘要翻译： 提供了门控半导体器件，其中主体具有在平行于衬底的主表面的横向方向上延伸的第一尺寸，以及在至少基本上垂直且至少基本垂直于主表面的方向上延伸的第二尺寸， 所述主体具有与所述第一侧相对的第一侧和第二侧。 门控半导体器件包括覆盖第一侧的第一栅极，并且在横向上具有第一栅极长度。 门控半导体器件还包括覆盖第二侧的第二栅极，第二栅极在横向上具有不同于第一栅极长度的第二栅极长度，并且优选地短于第一栅极长度。 在一个实施例中，第一栅极和第二栅极彼此电隔离。 在另一个实施例中，第一栅极主要由多晶硅锗组成，第二栅极主要由多晶硅组成。

公开(公告)号：US20060091450A1

公开(公告)日：2006-05-04

申请号：US10978951

申请日：2004-11-01

申请人： Huilong Zhu ,  Bruce Doris ,  Jochen Beintner

发明人： Huilong Zhu ,  Bruce Doris ,  Jochen Beintner

IPC分类号： H01L29/788 ,  H01L29/76

CPC分类号： H01L29/78684 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7881

摘要： A non-volatile storage cell in a Fin Field Effect Transistor (FinFET) and a method of forming an Integrated Circuit (IC) chip including the non-volatile storage cell. Each FET includes a control gate along one side of a semiconductor (e.g., silicon) fin, a floating gate along an opposite of the fin and a program gate alongside the floating gate. Control gate device thresholds are adjusted by adjusting charge on the floating gate.

公开(公告)号：US20080176365A1

公开(公告)日：2008-07-24

申请号：US12077973

申请日：2008-03-24

申请人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

发明人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

摘要： A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.

摘要翻译： 提供了一种制造门控半导体器件的方法。 这种方法可以包括图案化衬底的单晶半导体区域，以在与衬底的主表面平行的横向方向上延伸并且沿至少基本上垂直且至少基本垂直于主表面的方向延伸，半导体 区域具有第一侧和第二侧，例如远离第一侧。 第一栅极可以形成在第一侧上，第一栅极在横向上具有第一栅极长度。 第二栅极可以形成在第二侧上，第二栅极在横向上具有与第一栅极长度不同的第二栅极长度。 在一个实施例中，第二栅极长度可以比​​第一栅极长度短。 在一个实施例中，第一栅极可以主要由多晶硅锗组成，第二栅极可以由多晶硅组成。

公开(公告)号：US07785944B2

公开(公告)日：2010-08-31

申请号：US12077973

申请日：2008-03-24

申请人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

发明人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

IPC分类号： H01L21/84

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

摘要： A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.

摘要翻译： 提供了一种制造门控半导体器件的方法。 这种方法可以包括图案化衬底的单晶半导体区域，以在与衬底的主表面平行的横向方向上延伸并且沿至少基本上垂直且至少基本垂直于主表面的方向延伸，半导体 区域具有第一侧和第二侧，例如远离第一侧。 第一栅极可以形成在第一侧上，第一栅极在横向上具有第一栅极长度。 第二栅极可以形成在第二侧上，第二栅极在横向上具有与第一栅极长度不同的第二栅极长度。 在一个实施例中，第二栅极长度可以比​​第一栅极长度短。 在一个实施例中，第一栅极可以主要由多晶硅锗组成，第二栅极可以由多晶硅组成。

公开(公告)号：US07348641B2

公开(公告)日：2008-03-25

申请号：US10711182

申请日：2004-08-31

申请人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

发明人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

IPC分类号： H01L29/94

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

摘要： A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.

摘要翻译： 提供了门控半导体器件，其中主体具有在平行于衬底的主表面的横向方向上延伸的第一尺寸，以及在至少基本上垂直且至少基本垂直于主表面的方向上延伸的第二尺寸， 所述主体具有与所述第一侧相对的第一侧和第二侧。 门控半导体器件包括覆盖第一侧的第一栅极，并且在横向上具有第一栅极长度。 门控半导体器件还包括覆盖第二侧的第二栅极，第二栅极在横向上具有不同于第一栅极长度的第二栅极长度，并且优选地短于第一栅极长度。 在一个实施例中，第一栅极和第二栅极彼此电隔离。 在另一个实施例中，第一栅极主要由多晶硅锗组成，第二栅极主要由多晶硅组成。

公开(公告)号：US07091566B2

公开(公告)日：2006-08-15

申请号：US10717737

申请日：2003-11-20

申请人： Huilong Zhu ,  Jochen Beintner ,  Bruce B. Doris ,  Ying Zhang

发明人： Huilong Zhu ,  Jochen Beintner ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7856

摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.

摘要翻译： 包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 每个FET包括沿半导体（例如，硅）翅片的一侧的器件栅极和沿鳍片相对的背偏置栅极。 背偏置栅极电介质的不同之处在于器件栅极电介质的材料和/或厚度。 可以通过调整背偏置栅极电压来调整器件阈值。

公开(公告)号：US20080090366A1

公开(公告)日：2008-04-17

申请号：US11870436

申请日：2007-10-11

申请人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L21/336

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US20060043421A1

公开(公告)日：2006-03-02

申请号：US10711200

申请日：2004-09-01

申请人： Bruce Doris ,  Oleg Gluschenkov ,  Ying Zhang ,  Huilong Zhu

发明人： Bruce Doris ,  Oleg Gluschenkov ,  Ying Zhang ,  Huilong Zhu

IPC分类号： H01L27/10

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.

摘要翻译： 多栅极器件具有用于栅极顶部沟道的高k电介质层和用于finFET器件的保护层。 高k电介质层被放置在finFET的沟道的顶表面上，并且可以减少或消除沟道中的硅消耗。 在顶表面上使用高k电介质层减少了与高k电介质相关的滞后和迁移率降低。 保护层可以在蚀刻过程中保护高k电介质层。

公开(公告)号：US20050164433A1

公开(公告)日：2005-07-28

申请号：US11083743

申请日：2005-03-18

申请人： Bruce Doris ,  Thomas Kanarsky ,  Ying Zhang ,  Huilong Zhu ,  Meikei Ieong ,  Omer Dokumaci

发明人： Bruce Doris ,  Thomas Kanarsky ,  Ying Zhang ,  Huilong Zhu ,  Meikei Ieong ,  Omer Dokumaci

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6656 ,  H01L29/78612 ,  H01L29/78621

摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.