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    Method and apparatus for performing bringup simulation in a mobile terminal
    2.
    发明申请
    Method and apparatus for performing bringup simulation in a mobile terminal 审中-公开
    一种用于在移动终端中执行增强仿真的方法和装置

    公开(公告)号：US20050220044A1

    公开(公告)日：2005-10-06

    申请号：US11092714

    申请日：2005-03-30

    申请人： Kyu-Hyun Choi ,  Joon-Sang Ryu ,  Kyo-Sook Shin ,  Hun-Kee Kim ,  Joo-Kwang Kim

    发明人： Kyu-Hyun Choi ,  Joon-Sang Ryu ,  Kyo-Sook Shin ,  Hun-Kee Kim ,  Joo-Kwang Kim

    IPC分类号： H04B1/40 ,  H04B7/00 ,  H04M1/725

    CPC分类号： A63F13/65 ,  A63F13/10 ,  A63F13/12 ,  A63F13/217 ,  A63F13/332 ,  A63F13/58 ,  A63F13/63 ,  A63F13/825 ,  A63F2300/69 ,  A63F2300/8058 ,  H04M1/72544

    摘要： An apparatus and method for performing a bring-up simulation to bring up a character are provided. In the apparatus, a sensor measures at least one of an ambient temperature of the mobile terminal, a remaining battery power of the mobile terminal and an amount of vibrations of the mobile terminal, a controller compares the measured value received from the sensor with a predetermined threshold, calculates bonus points and penalty points according to the measured value, and controls the state of a character according to the calculated bonus and penalty points, character generator sets or updates the state of the character according to internal conditions of the mobile terminal, external conditions of the mobile terminal and user interaction with the character via the mobile terminal corresponding to a control signal received from the controller, and a display for displaying the character in accordance with the state and growth stage of the character.

    摘要翻译： 提供了一种用于执行提起模拟以提出字符的装置和方法。 在该装置中，传感器测量移动终端的环境温度，移动终端的剩余电池电量和移动终端的振动量中的至少一个，控制器将从传感器接收的测量值与预定的 阈值，根据测量值计算奖励积分和罚球点，并根据计算的奖金和罚球点，字符发生器设置或根据移动终端的内部条件来更新角色的状态来控制角色的状态，外部 移动终端的条件和用户经由移动终端与从控制器接收到的控制信号相对应的角色的交互，以及根据角色的状态和成长阶段显示角色的显示。

    Method of making stacked-capacitor for a dram cell same
    3.
    发明授权
    Method of making stacked-capacitor for a dram cell same 失效
    制作电容式电容器的方法

    公开(公告)号：US5236859A

    公开(公告)日：1993-08-17

    申请号：US804384

    申请日：1991-12-10

    申请人： Dong-Joo Bae ,  Won-Shik Baek ,  Kyu-Hyun Choi

    发明人： Dong-Joo Bae ,  Won-Shik Baek ,  Kyu-Hyun Choi

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/10817

    摘要： There is disclosed a stacked capacitor with high capacity which ensures structural stability in a DRAM cell and a method for manufacturing the same. The stacked-capacitor is of a hollow (or cylindrical) capacitor where both ends of several polysilicon layers which form a storage electrode are connected with each other. In construction, this inventive stacked-capacitor includes: a first polysilicon layer coupled to the source region so as to extend in parallel with surface of the substrate over the left and right sides of the source region; a bridge polysilicon layer, extending in the upward direction of the substrate from both ends of the first polysilicon layer; a dielectric film formed so as to contact with the surfaces of the bridge polysilicon layer, first polysilicon layer, second polysilicon layer; and a third polysilicon layer formed so as to contact with the surface of the dielectric film.

    摘要翻译： 公开了一种具有高容量的堆叠电容器，其确保DRAM单元中的结构稳定性及其制造方法。 堆叠式电容器是形成存储电极的多个多晶硅层的两端彼此连接的中空（或圆柱形）电容器。 在结构上，本发明的叠层电容器包括：第一多晶硅层，其耦合到源极区域，以在源极区域的左侧和右侧上平行于基板的表面延伸; 桥状多晶硅层，从所述第一多晶硅层的两端向所述基板的上方延伸; 形成为与桥多晶硅层，第一多晶硅层，第二多晶硅层的表面接触的电介质膜; 以及形成为与电介质膜的表面接触的第三多晶硅层。

    Method of making semiconductor devices having ohmic contact
    5.
    发明授权
    Method of making semiconductor devices having ohmic contact 失效
    制造具有欧姆接触的半导体器件的方法

    公开(公告)号：US5013686A

    公开(公告)日：1991-05-07

    申请号：US252514

    申请日：1988-09-30

    申请人： Kyu-Hyun Choi ,  Heyung-Sub Lee ,  Jung-Hwan Lee

    发明人： Kyu-Hyun Choi ,  Heyung-Sub Lee ,  Jung-Hwan Lee

    IPC分类号： H01L21/02 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78

    CPC分类号： H01L28/20 ,  H01L21/28525 ,  H01L21/76877 ,  H01L27/1112 ,  Y10S148/019 ,  Y10S148/147

    摘要： A method being capable of achieving the reduction in contact resistance between each layer when bringing a silicide layer into contact with a polycrystalline-silicon (polysilicon) layer in the manufacture of semiconductor devices. The method comprises the steps of forming a polysilicon layer and a silicide layer thereon over a partial top surface of a semiconductor substrate, forming an insulating layer over said silicide layer and the entire top surface of the substrate, forming a contact window by etching the partial area of the insulating layer over said silicide layer, and forming a polysilicon layer over the entire top surface of the substrate after performing ion-implantation through said contact window, wherein said ion-implantation is performed with N-type high doping into the silicide.

    摘要翻译： 一种在半导体器件的制造中使硅化物层与多晶硅（多晶硅）层接触时能够实现各层之间的接触电阻降低的方法。 该方法包括以下步骤：在半导体衬底的部分顶表面上形成多晶硅层和硅化物层，在所述硅化物层和衬底的整个顶表面上形成绝缘层，通过蚀刻部分 在所述硅化物层上的绝缘层的面积，以及在通过所述接触窗进行离子注入之后，在所述衬底的整个顶表面上形成多晶硅层，其中所述离子注入在所述硅化物中进行N型高掺杂。

    Semiconductor memory device with redundant block and cell array
    6.
    发明授权
    Semiconductor memory device with redundant block and cell array 失效
    具有冗余块和单元阵列的半导体存储器件

    公开(公告)号：US5297085A

    公开(公告)日：1994-03-22

    申请号：US800701

    申请日：1991-12-02

    申请人： Kyu-Hyun Choi ,  Hyun -Kun Byun ,  Jung-Ryul Lee ,  Choong-Kun Kwak

    发明人： Kyu-Hyun Choi ,  Hyun -Kun Byun ,  Jung-Ryul Lee ,  Choong-Kun Kwak

    IPC分类号： G11C11/413 ,  G11C11/40 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C29/787 ,  G11C29/808 ,  G11C29/78 ,  G11C29/781

    摘要： A semiconductor a semiconductor memory device including a plurality of normal blocks containing only normal memory cells without a redundant memory cell and a redundant block containing only redundant memory cells. The device comprises a plurality of normal blocks each having a plurality of normal row and column lines each connected with a plurality of normal memory cells; a redundant block having a plurality of redundant row and column lines each connected with a plurality of redundant memory cells; block decoder for selecting one of the normal blocks in response to first address signals; a redundant column decoder being programmed to select redundant columns replacing normal columns which are containing defective normal memory cells according to the output signals of the block decoder and second address signals, the decoder producing redundant operation signals when a defective normal memory cell is addressed; a redundant clock generator for producing a redundant control clock in response to the redundant operation signals; and a plurality of normal column decoders associated with the normal columns in the respective normal blocks, whereby the decoders all are disabled by the redundant control clock when a defective normal memory cell is addressed, and one of the decoders is enabled by the output signals of the block decoder for selecting a normal column line addressed by the second address signals when a defect-free normal memory cell is addressed.

    摘要翻译： 一种半导体半导体存储器件，包括仅包含不具有冗余存储单元的正常存储单元的多个正常块和仅包含冗余存储单元的冗余块。 该装置包括多个正常块，每个正常块具有多个正常行和列线，每个正常行和列线与多个正常存储单元连接; 具有多个冗余行和列线的冗余块，每个冗余行和列线与多个冗余存储器单元相连; 块解码器，用于响应于第一地址信号选择一个正常块; 冗余列解码器被编程为根据块解码器和第二地址信号的输出信号选择冗余列替换包含有缺陷的正常存储器单元的正常列，所述解码器在缺陷正常存储单元被寻址时产生冗余操作信号; 冗余时钟发生器，用于响应冗余操作信号产生冗余控制时钟; 以及与各个正常块中的常规列相关联的多个正常列解码器，由此当寻址有缺陷的正常存储单元时，所述解码器全部被冗余控制时钟禁用，并且解码器中的一个通过输出信号 块解码器，用于当寻找无缺陷的正常存储单元时，选择由第二地址信号寻址的普通列线。

    Stacked-capacitor for a DRAM cell
    7.
    发明授权
    Stacked-capacitor for a DRAM cell 失效
    用于DRAM单元的堆叠电容器

    公开(公告)号：US5095346A

    公开(公告)日：1992-03-10

    申请号：US575666

    申请日：1990-08-31

    申请人： Dong-Joo Bae ,  Won-Shik Baek ,  Kyu-Hyun Choi

    发明人： Dong-Joo Bae ,  Won-Shik Baek ,  Kyu-Hyun Choi

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/10817

    摘要： There is disclosed a stacked capacitor with high capacity which ensures structural stability in a DRAM cell and a method for manufacturing the same. The stacked-capacitor is of a hollow (or cylindrical) capacitor where both ends of several polysilicon layers which form a storage electrode are connected with each other. In construction, this inventive stacked-capacitor includes: a first polysilicon layer coupled to the source region so as to extend in parallel with surface of the substrate over the left and right sides of the source region; a bridge polysilicon layer, extending in the upward direction of the substrate from both ends of the first polysilicon layer; a dielectric film formed so as to contact with the surfaces of the bridge polysilicon layer, first polysilicon layer, second polysilicon layer; and a third polysilicon layer formed so as to contact with the surface of the dielectric film.

    摘要翻译： 公开了一种具有高容量的堆叠电容器，其确保DRAM单元中的结构稳定性及其制造方法。 堆叠式电容器是形成存储电极的多个多晶硅层的两端彼此连接的中空（或圆柱形）电容器。 在结构上，本发明的叠层电容器包括：第一多晶硅层，其耦合到源极区域，以在源极区域的左侧和右侧上平行于基板的表面延伸; 桥状多晶硅层，从所述第一多晶硅层的两端向所述基板的上方延伸; 形成为与桥多晶硅层，第一多晶硅层，第二多晶硅层的表面接触的电介质膜; 以及形成为与电介质膜的表面接触的第三多晶硅层。

    Static random access memory device with voltage control circuit
    8.
    发明授权
    Static random access memory device with voltage control circuit 失效
    具有电压控制电路的静态随机存取存储器件

    公开(公告)号：US4964084A

    公开(公告)日：1990-10-16

    申请号：US292449

    申请日：1988-12-30

    申请人： Tae-Sung Jung ,  Kyu-Hyun Choi

    发明人： Tae-Sung Jung ,  Kyu-Hyun Choi

    IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/40 ,  G11C11/407 ,  G11C11/417

    CPC分类号： G11C5/147 ,  G11C11/417 ,  G11C5/143

    摘要： SRAM device having a power supply voltage control circuit capable of preventing the failure of memory cells used for a long period of time, without lowering a power supply voltage is disclosed. The SRAM device includes a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells each coupled between a word line and each pair of bit lines, and a power supply regulating stage coupled to each memory cell, for decreasing a supply voltage delivered to each memory cell when an external power supply voltage exceeds a specified voltage level, and delivering the external power supply voltage to each memory cell when the external power supply voltage does not exceed the specified voltage level. If an external power supply voltage is lower than a voltage level Vc, the supply voltage is supplied as a power source of the memory cell. However, when the external power supply voltage exceeds the voltage level Vc, there is supplied a voltage of common power supply line lower than the power supply voltage by a threshold voltage of a MOS transistor.

    摘要翻译： 公开了具有能够防止长时间使用的存储单元的故障而不降低电源电压的电源电压控制电路的SRAM装置。 SRAM器件包括多个字线，多对位线，每个耦合在字线和每对位线之间的多个存储单元，以及耦合到每个存储器单元的电源调节级，用于减小 当外部电源电压超过规定的电压电平时，向每个存储单元输送的电源电压;以及当所述外部电源电压不超过规定的电压电平时，将外部电源电压输送给各个存储单元。 如果外部电源电压低于电压电平Vc，则作为存储单元的电源供给电源电压。 然而，当外部电源电压超过电压电平Vc时，通过MOS晶体管的阈值电压，提供比电源电压低的公共电源线的电压。