公开(公告)号：US5734598A

公开(公告)日：1998-03-31

申请号：US367028

申请日：1994-12-28

申请人： William L. Abbott ,  Hung C. Nguyen

发明人： William L. Abbott ,  Hung C. Nguyen

IPC分类号： G11B5/09 ,  G11B20/10 ,  H03H9/02 ,  H03H21/00 ,  G06F17/00

CPC分类号： H03H21/0012 ,  G11B20/10009 ,  H03H2021/007 ,  H03H2021/0078

摘要： An adaptive filter for use in disk drive systems includes coefficient adaptation circuitry operating at a slower rate than the filter and consequently at a reduced power level. The adaptive filter receives input data samples corresponding to raw data read from a disk in the disk drive system and converted to digital form and provides processed output data samples. The action of the filter is defined by characteristic filter coefficients having values that are updated by adaptation circuitry during the operation of the filter. The adaptive filter is independently clocked from the adaptation circuitry, such that the input data samples and the processed output data samples are clocked through the adaptive filter at a clock rate 1/T, and the filter coefficients are updated according to a prescribed algorithm at an update rate slower than the 1/T clock rate. Filter coefficient updating occurs preferably at a rate equal to 1/J, where J is an integer greater than unity and generally in the range of 2 to 8. The coefficient update rate is achieved by providing a separate filter coefficient adaptation clock derived from the system clock by dividing that clock by a user-programmable parameter J. This process reduces the coefficient update rate, which in turn reduces the switching frequency of the logic gates, the number of pipeline latches, and, ultimately, the power consumption.

摘要翻译： 用于磁盘驱动器系统的自适应滤波器包括以比滤波器更慢的速率运行的系数适配电路，因此在降低的功率电平。 自适应滤波器接收对应于从磁盘驱动器系统中的磁盘读取的原始数据的输入数据样本，并将其转换为数字形式并提供已处理的输出数据样本。 滤波器的动作由具有由滤波器操作期间的适配电路更新的值的特征滤波器系数定义。 自适应滤波器独立地从适配电路计时，使得输入数据样本和经处理的输出数据样本以时钟速率1 / T通过自适应滤波器计时，并且滤波器系数根据规定的算法在 更新速度比1 / T时钟速率慢。 滤波器系数更新优选地以等于1 / J的速率发生，其中J是大于1的整数，通常在2至8的范围内。系数更新速率通过提供从系统导出的单独的滤波器系数适配时钟来实现 通过将该时钟除以用户可编程参数J的时钟。该处理降低了系数更新速率，这又降低了逻辑门的开关频率，流水线锁存器的数量，以及最终的功耗。

公开(公告)号：US5375145A

公开(公告)日：1994-12-20

申请号：US936742

申请日：1992-08-27

申请人： William L. Abbott ,  Kenneth E. Johnson ,  Hung C. Nguyen

发明人： William L. Abbott ,  Kenneth E. Johnson ,  Hung C. Nguyen

IPC分类号： G11B20/10 ,  G11B20/12 ,  H04L25/49 ,  H04L27/08

CPC分类号： H04L25/4908 ,  G11B20/10 ,  G11B20/1258

摘要： A multi-mode gain control loop for a PR4, ML data channel, such as one included in a magnetic disk data storage device, includes an input for receiving from a source an analog signal stream including coded data to be detected; a VGA for amplifying the analog signal stream; an analog to digital converter for receiving the analog signal stream and for generating and putting out data samples therefrom; an analog gain control loop connected to generate an analog gain control from the analog data stream during a data non-read mode of the channel, to store the analog gain control in a storage circuit, and to apply the stored analog gain control constantly to control the VGA; and a digital gain control loop connected to generate gain vernier correction values from the data samples and for applying the gain vernier correction values through a gain DAC to provide an offset control to the VGA during a data read mode of the channel.

摘要翻译： 用于诸如包括在磁盘数据存储装置中的PR4，ML数据通道的多模式增益控制回路包括用于从源接收包括要检测的编码数据的模拟信号流的输入; 用于放大模拟信号流的VGA; 模数转换器，用于接收模拟信号流并从中产生和输出数据样本; 模拟增益控制回路，其被连接以在通道的数据非读取模式期间从模拟数据流生成模拟增益控制，以将模拟增益控制存储在存储电路中，并且持续地应用所存储的模拟增​​益控制以控制 VGA; 以及数字增益控制回路，其连接以从数据样本产生增益游标校正值，并通过增益DAC施加增益游标校正值，以在通道的数据读取模式期间向VGA提供偏移控制。

公开(公告)号：US5422760A

公开(公告)日：1995-06-06

申请号：US291957

申请日：1994-08-17

申请人： William L. Abbott ,  Hung C. Nguyen ,  Kenneth E. Johnson

发明人： William L. Abbott ,  Hung C. Nguyen ,  Kenneth E. Johnson

IPC分类号： G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  H03M13/23 ,  H04L25/49 ,  G11B5/09 ,  G11B5/035 ,  G11B27/10

CPC分类号： G11B20/10 ,  H04L25/4908 ,  G11B20/1258

摘要： A class IV partial response, maximum likelihood data channel for a disk drive includes an encoder connected to a data sequencer for converting user data blocks into a predetermined 8/9ths code such as a (0,4,4,) code. A precoder conveys the 8/9ths code into class IV code. An analog write driver supplies the class IV code to a data transducer head during data write-to-disk operations. A read channel connected to the head amplifies and conditions analog signals during data read operations. A quantizer produces samples of the analog signals in accordance with a quantization clock generated by a clock generator. An adaptive FIR filter means is conditions the data samples in accordance with selectable, adaptive filter coefficients. A Viterbi detector puts out the class IV code from the filtered and quantized samples. A postcoder conveys the detected class IV code into detected 8/9ths code. A decoder converts the detected 8/9ths code into user data and supplies user data to the sequencer. The programmable FIR filter is provided with servo coefficients during reading of the servo sectors, and an asynchronous servo detector detects head position information from the quantized and filtered samples without phase locking of the quantization clock generator to the quantized servo samples. The asynchronous servo detector is also used to aid detection of sync field preamble information before the FIR filter is fully adapted. Multi-mode gain and timing loops are also a part of the present invention.

摘要翻译： 用于磁盘驱动器的IV类部分响应，最大似然数据通道包括连接到数据定序器的编码器，用于将用户数据块转换成诸如（0,4,4）代码的预定的8/9代码。 预编码器将8/9代码传送到IV类代码。 模拟写入驱动器在数据写入到磁盘操作期间将IV类代码提供给数据传感器头。 连接到头的读通道在数据读取操作期间放大和调节模拟信号。 量化器根据由时钟发生器产生的量化时钟产生模拟信号的样本。 自适应FIR滤波器装置根据可选择的自适应滤波器系数来调节数据样本。 维特比检测器从滤波和量化样本中提取出IV类码。 后检测器将检测到的IV类代码传送到检测到的8/9代码。 解码器将检测到的8/9代码转换成用户数据，并将用户数据提供给定序器。 可编程FIR滤波器在读取伺服扇区期间提供伺服系数，并且异步伺服检测器从量化和滤波的采样中检测头位置信息，而不将量化时钟发生器锁定到量化的伺服采样。 异步伺服检测器还用于在FIR滤波器完全适配之前辅助检测同步字段前导码信息。 多模式增益和定时回路也是本发明的一部分。

公开(公告)号：US5381359A

公开(公告)日：1995-01-10

申请号：US936761

申请日：1992-08-27

申请人： William L. Abbott ,  Hung C. Nguyen

发明人： William L. Abbott ,  Hung C. Nguyen

IPC分类号： G11B20/10 ,  G11B20/12 ,  H04L25/49 ,  G06F7/38 ,  H03H7/30

CPC分类号： G11B20/10 ,  H04L25/4908 ,  G11B20/1258

摘要： A digital adaptive finite impulse response filter circuit is provided for a PR4,ML sampled data channel including an analog to digital sampler for providing raw digital samples of data to the filter circuit and a sampled data detector for detecting coded data from conditioned digital samples received from the filter circuit. The filter circuit comprises a multi-tap transversal filter structure wherein each tap is connected to receive a selected coefficient, a source of a plurality of coefficients for each tap, a coefficient selector connected to the source to receive the plurality of coefficients and to provide a selected coefficient to each tap of the transversal filter structure, and a control circuit for controlling the coefficient selector and the source for providing each of the selected coefficients to a corresponding tap of the transversal filter structure. Training and adaptation methods and circuits for adapting the filter structure are also described.

摘要翻译： 为包括模拟数字采样器的PR4，ML采样数据通道提供数字自适应有限脉冲响应滤波器电路，用于向滤波电路提供数据的原始数字采样，以及采样数据检测器，用于检测从 滤波电路。 滤波器电路包括多抽头横向滤波器结构，其中每个抽头被连接以接收所选择的系数，用于每个抽头的多个系数的源;连接到源以接收多个系数的系数选择器， 选择的系数到横向滤波器结构的每个抽头，以及控制电路，用于控制系数选择器和源，以将每个所选择的系数提供给横向滤波器结构的对应抽头。 还描述了用于适配滤波器结构的训练和适应方法和电路。

公开(公告)号：US5341249A

公开(公告)日：1994-08-23

申请号：US937064

申请日：1992-08-27

申请人： William L. Abbott ,  Hung C. Nguyen ,  Kenneth E. Johnson

发明人： William L. Abbott ,  Hung C. Nguyen ,  Kenneth E. Johnson

IPC分类号： G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  H03M13/23 ,  H04L25/49 ,  G11B5/09

CPC分类号： G11B20/10 ,  H04L25/4908 ,  G11B20/1258

摘要： A class IV partial response, maximum likelihood data channel for a disk drive includes an encoder connected to a data sequencer for converting user data blocks into a predetermined 8/9ths code such as a (0,4,4,) code. A precoder converts the 8/9ths code into class IV code. An analog write driver supplies the class IV code to a data transducer head during data write-to-disk operations. A read channel connected to the head amplifies and conditions analog signals during data read operations. A quantizer produces samples of the analog signals in accordance with a quantization clock generated by a clock generator. An adaptive FIR filter means is conditions the data samples in accordance with selectable, adaptive filter coefficients. A Viterbi detector puts out the class IV code from the filtered and quantized samples. A postcoder converts the detected class IV code into detected 8/9ths code. A decoder converts the detected 8/9ths code into user data and supplies user data to the sequencer. The programmable FIR filter is provided with servo coefficients during reading of the servo sectors, and an asynchronous servo detector detects head position information from the quantized and filtered samples without phase locking of the quantization clock generator to the quantized servo samples. The asynchronous servo detector is also used to aid detection of sync field preamble information before the FIR filter is fully adapted. Multi-mode gain and timing loops are also a part of the present invention.

摘要翻译： 用于磁盘驱动器的IV类部分响应，最大似然数据通道包括连接到数据定序器的编码器，用于将用户数据块转换成诸如（0,4,4）代码的预定的8/9代码。 预编码器将8/9代码转换为IV类代码。 模拟写入驱动器在数据写入到磁盘操作期间将IV类代码提供给数据传感器头。 连接到头的读通道在数据读取操作期间放大和调节模拟信号。 量化器根据由时钟发生器产生的量化时钟产生模拟信号的样本。 自适应FIR滤波器装置根据可选择的自适应滤波器系数来调节数据样本。 维特比检测器从滤波和量化的样本中输出IV类码。 后检测器将检测到的IV类代码转换为检测到的8/9代码。 解码器将检测到的8/9代码转换成用户数据，并将用户数据提供给定序器。 可编程FIR滤波器在读取伺服扇区期间提供伺服系数，并且异步伺服检测器从量化和滤波的采样中检测头位置信息，而不将量化时钟发生器锁定到量化的伺服采样。 异步伺服检测器还用于在FIR滤波器完全适配之前辅助检测同步字段前导码信息。 多模式增益和定时回路也是本发明的一部分。

公开(公告)号：US5258933A

公开(公告)日：1993-11-02

申请号：US936756

申请日：1992-08-27

申请人： Kenneth E. Johnson ,  William L. Abbott ,  Hung C. Nguyen

发明人： Kenneth E. Johnson ,  William L. Abbott ,  Hung C. Nguyen

IPC分类号： G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  H04L7/02 ,  H04L7/04 ,  H04L7/08 ,  H04L7/10 ,  G06J1/00 ,  G06F15/31

CPC分类号： H04L7/0054 ,  G11B20/10009 ,  G11B20/10055 ,  G11B20/10175 ,  G11B20/1258 ,  G11B20/1403 ,  H04L7/08 ,  G11B2020/1282 ,  H04L7/046 ,  H04L7/10

摘要： A multi-mode timing loop for a PR4,ML sampled data channel includes an analog to digital converter and a digital finite impulse response filter for providing conditioned digital samples. The timing loop includes a reference clock source for putting out a reference clock frequency related to a nominal sample data rate, a frequency controllable oscillator connected to generate a sample clock, an analog timing loop and a digital timing loop. The analog timing loop provides phase lock during non-data read mode, and during data read mode the digital timing loop provides a vernier offset for fine adjustment of phase lock to a static setting then provided by the analog timing loop.

摘要翻译： 用于PR4，ML采样数据信道的多模式定时环路包括模数转换器和用于提供调节数字样本的数字有限脉冲响应滤波器。 定时环路包括用于输出与标称采样数据速率相关的参考时钟频率的参考时钟源，连接以产生采样时钟的频率可控振荡器，模拟定时环路和数字定时环路。 模拟定时回路在非数据读取模式下提供相位锁定，在数据读取模式期间，数字定时回路提供一个游标偏移量，用于将相位锁定的精细调整到由模拟定时回路提供的静态设置。

公开(公告)号：US5345342A

公开(公告)日：1994-09-06

申请号：US192146

申请日：1994-02-04

申请人： William L. Abbott ,  Hung C. Nguyen ,  Kenneth E. Johnson

发明人： William L. Abbott ,  Hung C. Nguyen ,  Kenneth E. Johnson

IPC分类号： G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  H03M13/23 ,  H04L25/49 ,  G11B5/09 ,  G11B5/596

CPC分类号： G11B20/10 ,  H04L25/4908 ,  G11B20/1258

摘要： A class IV partial response, maximum likelihood data channel for a disk drive includes an encoder connected to a data sequencer for converting user data blocks into a predetermined 8/9ths code such as a (0,4,4,) code. A precoder converts the 8/9ths code into class IV code. An analog write driver supplies the class IV code to a data transducer head during data write-to-disk operations. A read channel connected to the head amplifies and conditions analog signals during data read operations. A quantizer produces samples of the analog signals in accordance with a quantization clock generated by a clock generator. An adaptive FIR filter means is conditions the data samples in accordance with selectable, adaptive filter coefficients. A Viterbi detector puts out the class IV code from the filtered and quantized samples. A postcoder converts the detected class IV code into detected 8/9ths code. A decoder converts the detected 8/9ths code into user data and supplies user data to the sequencer. The programmable FIR filter is provided with servo coefficients during reading of the servo sectors, and an asynchronous servo detector detects head position information from the quantized and filtered samples without phase locking of the quantization clock generator to the quantized servo samples. The asynchronous servo detector is also used to aid detection of sync field preamble information before the FIR filter is fully adapted. Multi-mode gain and timing loops are also a part of the present invention.

摘要翻译： 用于磁盘驱动器的IV类部分响应，最大似然数据通道包括连接到数据定序器的编码器，用于将用户数据块转换成诸如（0,4,4）代码的预定的8/9代码。 预编码器将8/9代码转换为IV类代码。 模拟写入驱动器在数据写入到磁盘操作期间将IV类代码提供给数据传感器头。 连接到头的读通道在数据读取操作期间放大和调节模拟信号。 量化器根据由时钟发生器产生的量化时钟产生模拟信号的样本。 自适应FIR滤波器装置根据可选择的自适应滤波器系数来调节数据样本。 维特比检测器从滤波和量化的样本中输出IV类码。 后检测器将检测到的IV类代码转换为检测到的8/9代码。 解码器将检测到的8/9代码转换成用户数据，并将用户数据提供给定序器。 可编程FIR滤波器在读取伺服扇区期间提供伺服系数，并且异步伺服检测器从量化和滤波的采样中检测头位置信息，而不将量化时钟发生器锁定到量化的伺服采样。 异步伺服检测器还用于在FIR滤波器完全适配之前辅助检测同步字段前导码信息。 多模式增益和定时回路也是本发明的一部分。

公开(公告)号：US5321559A

公开(公告)日：1994-06-14

申请号：US937352

申请日：1992-08-27

申请人： Hung C. Nguyen ,  William L. Abbott

发明人： Hung C. Nguyen ,  William L. Abbott

IPC分类号： G11B5/012 ,  G11B20/10 ,  G11B20/12 ,  H04L25/49 ,  G11B5/09 ,  G11B5/035

CPC分类号： G11B20/10 ,  H04L25/4908 ,  G11B20/1258 ,  G11B5/012

摘要： A digital peak detection circuit asynchronously detects embedded overhead information such as servo or sync pattern data within a PR4,ML synchronous data detection channel of a magnetic disk drive. The channel includes an analog to digital converter clocked by a data clock operating asynchronously with respect to playback of the embedded overhead information in the channel for converting an analog data stream into raw data samples, and an adaptive digital FIR filter for conditioning the raw data samples into conditioned data samples in accordance with programmable filter coefficients. The digital peak detection circuit includes a filter adaptation circuit for programming the digital FIR filter to a bandwidth characteristic selected for the embedded overhead information, a plurality of tapped clock delays each connected in tandem to receive and progressively by a period related to said data clock to delay conditioned data samples of the embedded overhead information, a first comparison logic array connected to predetermined taps of said tapped data clock period delays for comparing said conditioned data samples of the embedded overhead information at said taps and for generating a first logical condition therefrom, a second comparison logic array connected to a predetermined tap of said tapped clock delay means and to a threshold-providing circuit, for comparing the conditioned data samples of the embedded overhead information at the taps with threshold values provided by the threshold-providing circuit and for generating a second logical condition therefrom, and a digital combining circuit for combining the first logical condition and the second logical condition in order to detect and put out the embedded overhead information. A fault tolerant sync pattern detection method and apparatus is also disclosed.

摘要翻译： 数字峰值检测电路在磁盘驱动器的PR4，ML同步数据检测通道内异步检测嵌入式开销信息，例如伺服或同步模式数据。 该通道包括一个模数转换器，由数据时钟异步运行，数据时钟相对于用于将模拟数据流转换为原始数据样本的通道中的嵌入式开销信息的重放，以及用于调节原始数据样本的自适应数字FIR滤波器 根据可编程滤波器系数到条件数据样本。 数字峰值检测电路包括滤波器适配电路，用于将数字FIR滤波器编程为针对嵌入式开销信息选择的带宽特性，多个抽头时钟延迟，每个抽头时钟延迟串联连接以逐渐接收与所述数据时钟相关的周期 延迟所述嵌入式开销信息的经调节的数据样本，连接到所述抽头数据时钟周期延迟的预定抽头的第一比较逻辑阵列，用于比较所述抽头处的嵌入开销信息的所述经调节的数据样本，并用于从其产生第一逻辑条件; 连接到所述抽头时钟延迟装置的预定抽头的第二比较逻辑阵列和阈值提供电路，用于将抽头处的嵌入开销信息的条件数据样本与由阈值提供电路提供的阈值进行比较， 第二个逻辑条件，和ad 用于组合第一逻辑条件和第二逻辑条件的数字组合电路，以便检测和推出嵌入式开销信息。 还公开了容错同步模式检测方法和装置。

公开(公告)号：US20080310565A1

公开(公告)日：2008-12-18

申请号：US11818099

申请日：2007-06-13

申请人： William L. Abbott ,  Yehuda Azenkot

发明人： William L. Abbott ,  Yehuda Azenkot

IPC分类号： H04B1/10

CPC分类号： H04L27/2605 ,  H04L25/0204 ,  H04L25/0216 ,  H04L27/2647 ,  H04L27/2662

摘要： A method of adjusting overlap-and-add length for zero-padded suffixes. The method includes, based on a channel impulse response, estimating an effective channel length. When the effective channel length is less than a default overlap-and-add length and greater than a minimum length, the method includes setting the overlap-and-add length to the effective channel length. When the effective channel length is less than the minimum length, the method includes setting the overlap-and-add length to the minimum length. When the effective channel length is greater than the default overlap-and-add length, the method includes setting the overlap-and-add length to the default overlap-and-add length.

摘要翻译： 调整零填充后缀的重叠和加长度的方法。 该方法包括基于信道脉冲响应来估计有效信道长度。 当有效信道长度小于默认的重叠和加长度并且大于最小长度时，该方法包括将重叠和添加长度设置为有效信道长度。 当有效通道长度小于最小长度时，该方法包括将重叠和加长度设置为最小长度。 当有效通道长度大于默认重叠长度时，该方法包括将重叠和添加长度设置为默认的重叠和添加长度。

公开(公告)号：US5430661A

公开(公告)日：1995-07-04

申请号：US801815

申请日：1991-12-02

申请人： Kevin D. Fisher ,  William L. Abbott ,  John M. Cioffi ,  Philip S. Bednarz

发明人： Kevin D. Fisher ,  William L. Abbott ,  John M. Cioffi ,  Philip S. Bednarz

IPC分类号： G11B20/10 ,  H03H15/00 ,  H03H17/00 ,  H03H21/00 ,  H04B3/04 ,  H04L25/03 ,  G06F17/00

CPC分类号： G11B20/10046 ,  G11B20/10009 ,  H04L25/03057

摘要： Adaptive decision feedback equalizer apparatus for processing information stored on disk or tape media or the like including a data input buffer (34), a gain acquisition circuit (42), a timing acquisition circuit (40) operative to generate timing error signals for controlling the sampling phase of the read signals input to the input buffer, a synchronizing circuit (44) for generating sync detect signals and polarity signals, an FIR filter (36) for generating linear filter output signals, register means (39), feedforward update logic (38) for adjusting the equalizer coefficient signals to develop updated coefficient signals, a dual ported RAM (50) for storing a plurality of the equalizer coefficient signals, feedback logic (48) responsive to the linear filter output signals, equalizer coefficient signals obtained from the RAM, and train data signals, and operative to compute the equalizer error signals and equalizer output signals, feedback update logic (52) for adjusting the values of the coefficient signals for input back to the RAM as update signals, steady-state timing logic (54), and a controller (46) responsive to the polarity signals and the sync detect signals and operative to generate the train data signals and mode control signals for causing the equalizer apparatus to operate in either a set-up/test mode or a run mode, whereby read signals input from a storage media are sampled, amplified and digitally processed to decode stored information bits with the result that, as compared to prior art systems, storage density may be increased and error rate decreased.

摘要翻译： 用于处理存储在磁盘或磁带介质等上的信息的自适应判决反馈均衡器装置，包括数据输入缓冲器（34），增益获取电路（42），定时获取电路（40），用于产生定时误差信号， 输入到输入缓冲器的读取信号的采样相位，用于产生同步检测信号和极性信号的同步电路（44），用于产生线性滤波器输出信号的FIR滤波器（36），寄存器装置（39），前馈更新逻辑 38），用于调整均衡器系数信号以产生更新的系数信号;双端口RAM（50），用于存储多个均衡器系数信号，响应于线性滤波器输出信号的反馈逻辑（48），从 RAM和训练数据信号，并且可操作以计算均衡器误差信号和均衡器输出信号，反馈更新逻辑（52）用于调整 用于作为更新信号输入到RAM的系数信号，稳态定时逻辑（54）和响应于极性信号和同步检测信号的控制器（46），并用于产生列车数据信号和模式控制信号 用于使均衡器装置在设置/测试模式或运行模式下操作，由此从存储介质输入的读取信号被采样，放大和数字处理以解码存储的信息位，结果是与之前的 艺术系统，存储密度可能会增加，错误率降低。