公开(公告)号：US20060031662A1

公开(公告)日：2006-02-09

申请号：US11246595

申请日：2005-10-07

申请人： Hung Nguyen ,  Mark Boike

发明人： Hung Nguyen ,  Mark Boike

IPC分类号： G06F9/44

CPC分类号： G06F11/348 ,  G06F2201/86 ,  G06F2201/88

摘要： A processor is disclosed including trace and profile logic for gathering and producing data corresponding to events occurring during instruction execution. In one embodiment, the trace and profile logic includes a serial queue for serializing data corresponding to a plurality of “discontinuity instructions” grouped together for simultaneous execution. A “discontinuity instruction” alters, or is executed as a result of an altering of, sequential instruction fetching.

摘要翻译： 公开了一种处理器，包括用于收集和产生与指令执行期间发生的事件相对应的数据的跟踪和简档逻辑。 在一个实施例中，跟踪和简档逻辑包括用于将与多个“不连续指令”相对应的数据串行化以用于同时执行的串行队列。 “不连续指令”改变或由于更改顺序指令取出而执行。

公开(公告)号：US20060156100A1

公开(公告)日：2006-07-13

申请号：US11023731

申请日：2004-12-28

申请人： Mark Boike ,  Seshagiri Kalluri ,  Vijayanand Angarai ,  David Brantley ,  Scott Beeker

发明人： Mark Boike ,  Seshagiri Kalluri ,  Vijayanand Angarai ,  David Brantley ,  Scott Beeker

IPC分类号： G01R31/28

CPC分类号： G01R31/318572

摘要： An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic design and operation of the hard macro are unknown. A test wrapper is embedded in the SOC. The test wrapper includes a scan chain. The test wrapper surrounds inputs and outputs of the hard macro. The test wrapper receives a known test data pattern in the scan chain that is included in the test wrapper. The hard macro receives from the test wrapper a set of non-test standard SOC inputs when the SOC is not in a test mode and receives the known test data pattern when the SOC is in the test mode. The hard macro generates a set of outputs in response to the inputs. The hard macro is tested utilizing the known test data pattern.

公开(公告)号：US06959376B1

公开(公告)日：2005-10-25

申请号：US09975677

申请日：2001-10-11

申请人： Mark Boike ,  Alan Phan ,  Keith Dang ,  Charles H. Stewart

发明人： Mark Boike ,  Alan Phan ,  Keith Dang ,  Charles H. Stewart

IPC分类号： G06F15/16 ,  G06F15/80

CPC分类号： G06F15/8007

摘要： The present invention is an integrated circuit containing multiple digital signal processors (DSPs). A single host processor interface is also placed on the chip to connect the multiple DSPs to the host. A separate direct memory access (DMA) unit is provided for each DSP to facilitate flow of data to and from a data memory for each DSP. Each DSP also includes an instruction memory.

摘要翻译： 本发明是一种包含多个数字信号处理器（DSP）的集成电路。 单个主机处理器接口也放置在芯片上，以将多个DSP连接到主机。 为每个DSP提供单独的直接存储器访问（DMA）单元，以促进数据到每个DSP的数据存储器和从数据存储器流出。 每个DSP还包括一个指令存储器。