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41 条记录 (耗时 0.027 秒)

    Phase jumping locked loop circuit
    2.
    发明授权
    Phase jumping locked loop circuit 有权
    相跳锁定回路电路

    公开(公告)号：US07135903B2

    公开(公告)日：2006-11-14

    申请号：US10374251

    申请日：2003-02-25

    申请人： Jade M. Kizer ,  Benedict C. Lau ,  Roxanne T. Vu ,  Huy M. Nguyen ,  Leung Yu ,  Adam Chuen-Huei Chou

    发明人： Jade M. Kizer ,  Benedict C. Lau ,  Roxanne T. Vu ,  Huy M. Nguyen ,  Leung Yu ,  Adam Chuen-Huei Chou

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0805 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0814

    摘要： A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines. The biasing circuit comprising a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.

    摘要翻译： 一个跳相锁定环路。 锁定环电路包括多个差分放大器和可切换地耦合到每个差分放大器的偏置电路。 每个差分放大器具有输入以接收耦合到公共输出信号线对的相应的一对时钟信号和输出。 偏置电路包括彼此并联并与第一组差分放大器串联耦合的第一多个偏置晶体管，以及第二组多个偏置晶体管，其彼此并联耦合并与第二组 差分放大器。

    Phase synchronization for wide area integrated circuits
    3.
    发明授权
    Phase synchronization for wide area integrated circuits 有权
    广域集成电路的相位同步

    公开(公告)号：US07932755B2

    公开(公告)日：2011-04-26

    申请号：US11620309

    申请日：2007-01-05

    申请人： Huy M. Nguyen ,  Benedict C. Lau ,  Leung Yu ,  Jade M. Kizer

    发明人： Huy M. Nguyen ,  Benedict C. Lau ,  Leung Yu ,  Jade M. Kizer

    IPC分类号： H03L7/06

    CPC分类号： G06F1/10 ,  G06F1/12 ,  H03L7/00

    摘要： A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.

    摘要翻译： 用于同步计时器件的电路和方法，例如寄存器。 由于不同的传播延迟，寄存器由具有相同频率但潜在不同相位的各个组件时钟信号计时。 通过对寄存器中的分量时钟信号的相位进行评估，使寄存器接收到的单独的分量时钟信号变为相位，并且将序列中的每个寄存器的分量时钟信号与先前寄存器的分量时钟信号同步。

    Phase synchronization for wide area integrated circuits
    4.
    发明授权
    Phase synchronization for wide area integrated circuits 有权
    广域集成电路的相位同步

    公开(公告)号：US07161400B2

    公开(公告)日：2007-01-09

    申请号：US10963698

    申请日：2004-10-13

    申请人： Huy M. Nguyen ,  Benedict C. Lau ,  Leung Yu ,  Jade M. Kizer

    发明人： Huy M. Nguyen ,  Benedict C. Lau ,  Leung Yu ,  Jade M. Kizer

    IPC分类号： H03L7/06

    CPC分类号： G06F1/10 ,  G06F1/12 ,  H03L7/00

    摘要： A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.

    摘要翻译： 用于同步计时器件的电路和方法，例如寄存器。 由于不同的传播延迟，寄存器由具有相同频率但潜在不同相位的各个组件时钟信号计时。 通过对寄存器中的分量时钟信号的相位进行评估，使寄存器接收到的单独的分量时钟信号变为相位，并且将序列中的每个寄存器的分量时钟信号与先前寄存器的分量时钟信号同步。

    Method and apparatus for low capacitance, high output impedance driver
    10.
    发明授权
    Method and apparatus for low capacitance, high output impedance driver 失效
    低电容，高输出阻抗驱动器的方法和装置

    公开(公告)号：US06330193B1

    公开(公告)日：2001-12-11

    申请号：US09539807

    申请日：2000-03-31

    申请人： Leung Yu ,  Roxanne T. Vu ,  Benedict C. Lau ,  Huy M. Nguyen ,  James A. Gasbarro

    发明人： Leung Yu ,  Roxanne T. Vu ,  Benedict C. Lau ,  Huy M. Nguyen ,  James A. Gasbarro

    IPC分类号： G11C700

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1084

    摘要： A method is described that compares two voltages, one of the voltages indicative of a data line voltage, a second of the voltages indicative of a reference voltage. An input signal is sent to each of a plurality of drivers where at least one of the drivers is coupled to the data line. The input signal is based upon the comparison. A bias is applied to a transistor from the input signal, the bias keeping the transistor in a high output impedance state when the two voltages are the same.

    摘要翻译： 描述了一种方法，其比较两个电压，指示数据线电压的电压之一，表示参考电压的第二电压。 输入信号被发送到多个驱动器中的至少一个驱动器耦合到数据线的每个驱动器。 输入信号基于比较。 从输入信号向晶体管施加偏压，当两个电压相同时，偏置保持晶体管处于高输出阻抗状态。