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公开(公告)号：US07979758B2
公开(公告)日：2011-07-12
申请号：US12154870
申请日：2008-05-28
申请人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
发明人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
CPC分类号： G11C29/12 , G11C11/401
摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.
摘要翻译： 半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元执行包括写入操作的多个内部操作来检测缺陷 在晶圆级别。
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公开(公告)号：US07808851B2
公开(公告)日：2010-10-05
申请号：US12474243
申请日：2009-05-28
申请人： Hwang Hur , Chang-Ho Do
发明人： Hwang Hur , Chang-Ho Do
IPC分类号： G11C29/00
CPC分类号： G11C29/26 , G11C8/16 , G11C11/401
摘要： A semiconductor memory device includes a read bus line for transferring read data; a write bus line for transferring write data; and a temporary data storage unit connected between the read bus line and the write bus line and controlled by a test mode signal enabled during a test mode.
摘要翻译： 半导体存储器件包括用于传送读取数据的读出总线; 用于传送写入数据的写入总线; 以及临时数据存储单元，连接在读总线和写总线之间，并由在测试模式期间启用的测试模式信号控制。
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公开(公告)号：US08225150B2
公开(公告)日：2012-07-17
申请号：US13149683
申请日：2011-05-31
申请人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
发明人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
CPC分类号： G11C29/12 , G11C11/401
摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.
摘要翻译： 半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元执行包括写入操作的多个内部操作来检测缺陷 在晶圆级别。
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公开(公告)号：US08054702B2
公开(公告)日：2011-11-08
申请号：US12472252
申请日：2009-05-26
申请人： Hwang Hur , Chang-Ho Do
发明人： Hwang Hur , Chang-Ho Do
IPC分类号： G11C7/00
CPC分类号： G11C29/34 , G11C7/1006 , G11C7/22 , G11C8/16 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C2207/108
摘要： A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in synchronization with a first clock signal of an internal clock, and transferring the input signals as second signals in synchronization with a second clock signal of the internal clock; a second transferring unit for transferring the first signals in synchronization with the second clock signal of the internal clock; and an aligning unit for aligning the first and second signals transferred from the first and second transferring units and outputting the aligned signal as output signals.
摘要翻译： 信号对准电路包括多个焊盘，1比特1比特并行地接收输入信号; 第一传送单元，用于将输入信号作为与内部时钟的第一时钟信号同步的第一信号传送，并且将输入信号作为与内部时钟的第二时钟信号同步的第二信号传送; 第二传送单元，用于与所述内部时钟的第二时钟信号同步地传送所述第一信号; 以及对准单元，用于对准从第一和第二传送单元传送的第一和第二信号，并输出对准的信号作为输出信号。
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公开(公告)号：US20100169583A1
公开(公告)日：2010-07-01
申请号：US12717011
申请日：2010-03-03
申请人： Jin-Il Chung , Jae-II Kim , Chang-Ho Do , Hwang Hur
发明人： Jin-Il Chung , Jae-II Kim , Chang-Ho Do , Hwang Hur
IPC分类号： G06F12/00
摘要： A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks.
摘要翻译： 多端口存储器件包括端口，存储体，全局数据总线，输入/输出（I / O）控制器，模式寄存器集（MRS），时钟发生器和测试I / O控制器。 I / O控制器响应于模式寄存器使能信号将测试信号发送到全局数据总线。 MRS响应于模式寄存器使能信号产生测试使能信号，并输出一个模式选择信号，该模式选择信号响应于测试信号确定测试I / O信号的数据传输模式。 时钟发生器响应于模式选择信号接收外部时钟并基于外部时钟生成内部时钟。 测试I / O控制器与内部时钟同步输入/输出测试I / O信号。 在测试操作模式期间模式寄存器使能信号有效，用于测试存储体的核心区域。
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公开(公告)号：US20090290436A1
公开(公告)日：2009-11-26
申请号：US12474243
申请日：2009-05-28
申请人： Hwang Hur , Chang-Ho Do
发明人： Hwang Hur , Chang-Ho Do
CPC分类号： G11C29/26 , G11C8/16 , G11C11/401
摘要： A semiconductor memory device includes a read bus line for transferring read data; a write bus line for transferring write data; and a temporary data storage unit connected between the read bus line and the write bus line and controlled by a test mode signal enabled during a test mode.
摘要翻译： 半导体存储器件包括用于传送读取数据的读出总线; 用于传送写入数据的写入总线; 以及临时数据存储单元，连接在读总线和写总线之间，并由在测试模式期间启用的测试模式信号控制。
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公开(公告)号：US20090231933A1
公开(公告)日：2009-09-17
申请号：US12472252
申请日：2009-05-26
申请人： Hwang Hur , Chang-Ho Do
发明人： Hwang Hur , Chang-Ho Do
CPC分类号： G11C29/34 , G11C7/1006 , G11C7/22 , G11C8/16 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C2207/108
摘要： A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in synchronization with a first clock signal of an internal clock, and transferring the input signals as second signals in synchronization with a second clock signal of the internal clock; a second transferring unit for transferring the first signals in synchronization with the second clock signal of the internal clock; and an aligning unit for aligning the first and second signals transferred from the first and second transferring units and outputting the aligned signal as output signals.
摘要翻译： 信号对准电路包括多个焊盘，1比特1比特并行地接收输入信号; 第一传送单元，用于将输入信号作为与内部时钟的第一时钟信号同步的第一信号传送，并且将输入信号作为与内部时钟的第二时钟信号同步的第二信号传送; 第二传送单元，用于与所述内部时钟的第二时钟信号同步地传送所述第一信号; 以及对准单元，用于对准从第一和第二传送单元传送的第一和第二信号，并输出对准的信号作为输出信号。
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公开(公告)号：US20090219775A1
公开(公告)日：2009-09-03
申请号：US12154870
申请日：2008-05-28
申请人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
发明人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
CPC分类号： G11C29/12 , G11C11/401
摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.
摘要翻译： 半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元执行包括写入操作的多个内部操作来检测缺陷 在晶圆级别。
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公开(公告)号：US20070074064A1
公开(公告)日：2007-03-29
申请号：US11524023
申请日：2006-09-19
申请人： Hwang Hur , Chang-Ho Do
发明人： Hwang Hur , Chang-Ho Do
IPC分类号： G06F11/00
CPC分类号： G11C29/26 , G11C8/16 , G11C11/401
摘要： A semiconductor memory device includes a read bus line for transferring read data; a write bus line for transferring write data; and a temporary data storage unit connected between the read bus line and the write bus line and controlled by a test mode signal enabled during a test mode.
摘要翻译： 半导体存储器件包括用于传送读取数据的读出总线; 用于传送写入数据的写入总线; 以及临时数据存储单元，连接在读总线和写总线之间，并由在测试模式期间启用的测试模式信号控制。
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公开(公告)号：US08031552B2
公开(公告)日：2011-10-04
申请号：US12717011
申请日：2010-03-03
申请人： Jin-Il Chung , Jae-Il Kim , Chang-Ho Do , Hwang Hur
发明人： Jin-Il Chung , Jae-Il Kim , Chang-Ho Do , Hwang Hur
IPC分类号： G11C8/00
摘要： A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks.
摘要翻译： 多端口存储器件包括端口，存储体，全局数据总线，输入/输出（I / O）控制器，模式寄存器集（MRS），时钟发生器和测试I / O控制器。 I / O控制器响应于模式寄存器使能信号将测试信号发送到全局数据总线。 MRS响应于模式寄存器使能信号产生测试使能信号，并输出一个模式选择信号，该模式选择信号响应于测试信号确定测试I / O信号的数据传输模式。 时钟发生器响应于模式选择信号接收外部时钟并基于外部时钟生成内部时钟。 测试I / O控制器与内部时钟同步输入/输出测试I / O信号。 在测试操作模式期间模式寄存器使能信号有效，用于测试存储体的核心区域。
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