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    MULTI-PORT MEMORY DEVICE WITH SERIAL INPUT/OUTPUT INTERFACE
    1.
    发明申请
    MULTI-PORT MEMORY DEVICE WITH SERIAL INPUT/OUTPUT INTERFACE 有权
    具有串行输入/输出接口的多端口存储器件

    公开(公告)号：US20100169583A1

    公开(公告)日：2010-07-01

    申请号：US12717011

    申请日：2010-03-03

    申请人： Jin-Il Chung ,  Jae-II Kim ,  Chang-Ho Do ,  Hwang Hur

    发明人： Jin-Il Chung ,  Jae-II Kim ,  Chang-Ho Do ,  Hwang Hur

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1075 ,  G11C7/22 ,  G11C7/222 ,  G11C8/16 ,  G11C29/26 ,  G11C29/32

    摘要： A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks.

    摘要翻译： 多端口存储器件包括端口，存储体，全局数据总线，输入/输出（I / O）控制器，模式寄存器集（MRS），时钟发生器和测试I / O控制器。 I / O控制器响应于模式寄存器使能信号将测试信号发送到全局数据总线。 MRS响应于模式寄存器使能信号产生测试使能信号，并输出一个模式选择信号，该模式选择信号响应于测试信号确定测试I / O信号的数据传输模式。 时钟发生器响应于模式选择信号接收外部时钟并基于外部时钟生成内部时钟。 测试I / O控制器与内部时钟同步输入/输出测试I / O信号。 在测试操作模式期间模式寄存器使能信号有效，用于测试存储体的核心区域。

    Wordline driving circuit of semiconductor memory device
    2.
    发明授权
    Wordline driving circuit of semiconductor memory device 失效
    半导体存储器件的字线驱动电路

    公开(公告)号：US07983097B2

    公开(公告)日：2011-07-19

    申请号：US12157236

    申请日：2008-06-09

    申请人： Jae-II Kim ,  Chang-Ho Do

    发明人： Jae-II Kim ,  Chang-Ho Do

    IPC分类号： G11C5/14

    CPC分类号： G11C8/08

    摘要： Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an over-driver configured to increase the threshold bias voltage at an initial stage of a data accessing operation and a wordline driver configured to activate a wordline in response to the threshold bias voltage and a signal output from the over-driver.

    摘要翻译： 半导体存储器件的字线驱动电路包括被配置为产生用于访问数据的阈值偏置电压的偏置发生器，被配置为在数据访问操作的初始阶段增加阈值偏置电压的过驱动器和被配置为激活 字线响应阈值偏置电压和从过驱动器输出的信号。

    Perfluorostyrene compound, and coating solution and optical waveguide device using the same
    4.
    发明授权
    Perfluorostyrene compound, and coating solution and optical waveguide device using the same 有权
    全氟苯乙烯化合物，以及使用其的涂布液和光波导装置

    公开(公告)号：US07202324B2

    公开(公告)日：2007-04-10

    申请号：US11034646

    申请日：2005-01-13

    申请人： Ji-Hyang Kim ,  Jae-II Kim ,  Tae-Kyun Kim ,  Hyung Jong Lee ,  Seon Gyu Han

    发明人： Ji-Hyang Kim ,  Jae-II Kim ,  Tae-Kyun Kim ,  Hyung Jong Lee ,  Seon Gyu Han

    IPC分类号： C08G65/40

    CPC分类号： C07C43/225 ,  C07C43/29 ,  C07C2603/18 ,  C08F214/18 ,  C09D4/00 ,  G02B6/138

    摘要： Disclosed is a fluorine compound having perfluorostyrene introduced at a terminal thereof, as represented in the following Formula 1, and a coating solution and an optical waveguide device using the same, characterized in that the introduction of perfluorostyrene results in a facile fabrication of thin films by a UV curing or a thermal curing, high thermal stability and chemical resistance, and low optical propagation loss and birefringence: Wherein Z is O or S; RF is an aliphatic or aromatic group; y is a natural number of 1–10; y′ is an integer of 0–1; x is an integer of 0–200; and Wherein B is a single bond or selected from the group consisting of —CO—, —SO2—, —S— and —O—, and Hal is selected from the group consisting of F, Cl, Br and I.

    摘要翻译： 公开了如下式1所示的具有全氟苯乙烯引入的氟化合物，其具有如下式1所示的涂布液和使用该氟化合物的光波导装置，其特征在于，全氟苯乙烯的引入导致薄膜的容易制造 UV固化或热固化，高热稳定性和耐化学性，以及低的光传播损耗和双折射：

    Latency control circuit, latency control method thereof, and semiconductor memory device including the same
    5.
    发明授权
    Latency control circuit, latency control method thereof, and semiconductor memory device including the same 有权
    延迟控制电路，其等待时间控制方法和包括该延迟控制电路的半导体存储器件

    公开(公告)号：US08446785B2

    公开(公告)日：2013-05-21

    申请号：US13207979

    申请日：2011-08-11

    申请人： Min-Su Park ,  Jae-II Kim

    发明人： Min-Su Park ,  Jae-II Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1072 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  H03L7/0814

    摘要： A latency control circuit of a semiconductor device includes a phase detection unit configured to generate phase information regarding a phase difference between an external clock and an internal clock, a delay amount deciding unit configured to decide a latency delay amount based on path information of an input signal, a latency value of the input signal, and the phase information, and a latency delay unit configured to generate a latency signal by delaying the input signal according to the latency delay amount and the phase information to produce a delayed input signal and by synchronizing the delayed input signal with the internal clock.

    摘要翻译： 半导体器件的等待时间控制电路包括相位检测单元，被配置为产生关于外部时钟和内部时钟之间的相位差的相位信息;延迟量判定单元，被配置为基于输入的路径信息来决定等待时间延迟量 信号，输入信号的延迟值和相位信息，以及等待时间延迟单元，被配置为通过根据延迟延迟量和相位信息延迟输入信号来产生等待时间信号，以产生延迟的输入信号，并通过同步 具有内部时钟的延迟输入信号。