公开(公告)号：US07088635B2

公开(公告)日：2006-08-08

申请号：US11027195

申请日：2004-12-30

申请人： Hwang Hur ,  Tae-Yun Kim

发明人： Hwang Hur ,  Tae-Yun Kim

IPC分类号： G11C7/00

CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622

摘要： A partial array self refresh (PASR) control apparatus for use in a semiconductor memory device having a plurality of banks includes: a bank deselection unit having a plurality of bank deselection signal output units for receiving a plurality of PASR code signals, wherein input terminal lines of each bank deselection signal output unit and signal lines of the plurality of PASR code signals are crossed each other and are selectively coupled each other.

摘要翻译： 一种用于具有多个存储体的半导体存储器件的部分阵列自刷新（PASR）控制装置包括：具有多个存储体取消信号输出单元的存储体取消选择单元，用于接收多个PASR编码信号，其中输入端子行 每个存储体取消选择信号输出单元和多个PASR码信号的信号线彼此交叉并且被选择性地彼此耦合。

公开(公告)号：US07493533B2

公开(公告)日：2009-02-17

申请号：US11017646

申请日：2004-12-22

申请人： Tae-Yun Kim ,  Hwang Hur ,  Jun-Gi Choi

发明人： Tae-Yun Kim ,  Hwang Hur ,  Jun-Gi Choi

IPC分类号： G11C29/00

CPC分类号： G11C29/50012 ,  G11C29/02 ,  G11C2029/0403

摘要： A delay detecting apparatus detects delay amounts of delay elements in a semiconductor device by using a test mode. The semiconductor device comprises a delay signal detecting unit for detecting delays of delay elements in the semiconductor device by using a signal that is synchronized with an external clock, and a delay signal outputting unit for outputting a delayed signal from the delay signal detecting unit to a data pad by using the signal that is synchronized with the external clock.

摘要翻译： 延迟检测装置通过使用测试模式来检测半导体器件中的延迟元件的延迟量。 半导体器件包括延迟信号检测单元，用于通过使用与外部时钟同步的信号来检测半导体器件中的延迟元件的延迟;以及延迟信号输出单元，用于将延迟信号从延迟信号检测单元输出到 通过使用与外部时钟同步的信号进行数据传输。

公开(公告)号：US20050229051A1

公开(公告)日：2005-10-13

申请号：US11017646

申请日：2004-12-22

申请人： Tae-Yun Kim ,  Hwang Hur ,  Jun-Gi Choi

发明人： Tae-Yun Kim ,  Hwang Hur ,  Jun-Gi Choi

IPC分类号： G11C29/00 ,  G11C29/02

CPC分类号： G11C29/50012 ,  G11C29/02 ,  G11C2029/0403

摘要： A delay detecting apparatus detects delay amounts of delay elements in a semiconductor device by using a test mode. The semiconductor device comprises a delay signal detecting unit for detecting delays of delay elements in the semiconductor device by using a signal that is synchronized with an external clock, and a delay signal outputting unit for outputting a delayed signal from the delay signal detecting unit to a data pad by using the signal that is synchronized with the external clock.

摘要翻译： 延迟检测装置通过使用测试模式来检测半导体器件中的延迟元件的延迟量。 半导体器件包括延迟信号检测单元，用于通过使用与外部时钟同步的信号来检测半导体器件中的延迟元件的延迟;以及延迟信号输出单元，用于将延迟信号从延迟信号检测单元输出到 通过使用与外部时钟同步的信号进行数据传输。

公开(公告)号：US20050270874A1

公开(公告)日：2005-12-08

申请号：US11027195

申请日：2004-12-30

申请人： Hwang Hur ,  Tae-Yun Kim

发明人： Hwang Hur ,  Tae-Yun Kim

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C11/406

CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622

摘要： A partial array self refresh (PASR) control apparatus for use in a semiconductor memory device having a plurality of banks includes: a bank deselection unit having a plurality of bank deselection signal output units for receiving a plurality of PASR code signals, wherein input terminal lines of each bank deselection signal output unit and signal lines of the plurality of PASR code signals are crossed each other and are selectively coupled each other.

摘要翻译： 一种用于具有多个存储体的半导体存储器件的部分阵列自刷新（PASR）控制装置包括：具有多个存储体取消信号输出单元的存储体取消选择单元，用于接收多个PASR编码信号，其中输入端子行 每个存储体取消选择信号输出单元和多个PASR码信号的信号线彼此交叉并且被选择性地彼此耦合。

公开(公告)号：US20120197122A1

公开(公告)日：2012-08-02

申请号：US13108427

申请日：2011-05-16

申请人： Sandstrom Kurt ,  Dae Young Kim ,  Soo Hwan Shin ,  Tae-Yun Kim

发明人： Sandstrom Kurt ,  Dae Young Kim ,  Soo Hwan Shin ,  Tae-Yun Kim

IPC分类号： A61B8/00

CPC分类号： A61B8/54 ,  A61B8/4444 ,  A61B8/465 ,  A61B8/467 ,  A61B8/56 ,  A61B8/585 ,  G01S7/5205

摘要： Provided is a method of controlling voltage levels of overall outputs in a combinational mode, in an ultrasonic diagnosis apparatus that may operate in the combinational mode. A judging unit of the ultrasonic diagnosis apparatus may judge whether at least a part of individual modes included in the combinational mode exceeds a threshold determined by safety standards, in accordance with an inputted overall output voltage level control command. When it is judged that at least the part of the individual modes exceeds the threshold determined by the safety standards, an output control unit may maintain an individual output with respect to the at least the part, among the voltage levels that may be outputted from a transducer, to be below the threshold, so that the individual output may be below the standards in accordance with the overall output control command.

摘要翻译： 提供了一种在组合模式中可以操作的超声波诊断装置中控制组合模式的总输出的电压电平的方法。 超声波诊断装置的判断单元可以根据输入的总输出电压电平控制指令来判断组合模式中包括的各个模式的至少一部分是否超过由安全标准确定的阈值。 当判定至少部分单个模式超过由安全标准确定的阈值时，输出控制单元可以相对于至少该部分保持可输出的电压中的至少一部分的单独输出 传感器低于阈值，使得单个输出可以根据总输出控制命令低于标准。

公开(公告)号：US07568263B2

公开(公告)日：2009-08-04

申请号：US11101456

申请日：2005-04-08

申请人： Tae-Yun Kim ,  Jong-Gun Bae

发明人： Tae-Yun Kim ,  Jong-Gun Bae

IPC分类号： A44C5/00 ,  A44C5/14

CPC分类号： G04G17/02 ,  G04B37/1486 ,  H04B1/385 ,  Y10T24/4718 ,  Y10T24/4782

摘要： A hinge apparatus includes a substantially cylindrical holder having at least one guide hole with a predetermined degree slope that extends in a longitudinal direction. A hinge shaft includes a substantially cylindrical surface configured to linearly move in the longitudinal direction of the holder. A guide pin has an end located inside the guide hole and is configured to extend through the cylindrical surface of the hinge shaft. Therefore, when the hinge shaft moves linearly in the holder, the guide pin moves along the guide hole so that the hinge shaft rotates in the holder.

摘要翻译： 铰链装置包括基本上圆柱形的保持器，其具有至少一个沿纵向方向延伸的预定斜度的引导孔。 铰链轴包括基本上圆柱形的表面，其构造成沿着保持器的纵向方向线性移动。 引导销具有位于引导孔内部的端部，并且构造成延伸穿过铰链轴的圆柱形表面。 因此，当铰链轴在保持架中线性移动时，引导销沿着引导孔移动，使得铰链轴在保持器中旋转。

公开(公告)号：US07263013B2

公开(公告)日：2007-08-28

申请号：US10880831

申请日：2004-06-29

申请人： Tae-Yun Kim

发明人： Tae-Yun Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/12

摘要： A memory device for adjusting a write recovery time includes a synchronous write recovery time controlling block which receives a control signal for performing an auto-precharge operation and delays out the control signal as long as a certain clock section of the operational clock corresponding to the write recovery time, an asynchronous write recovery time controlling block for delaying out the control signal coupled thereto as long as a fixed delay time corresponding to the write recovery time, a selecting block for choosing the synchronous write recovery time controlling block or the asynchronous write recovery time controlling block, and an auto-precharge controlling block which outputs as an auto-precharge execution signal used in performing the auto-precharge operation a signal outputted from the synchronous write recovery time controlling block or the asynchronous write recovery time controlling block in response to a write command.

摘要翻译： 用于调整写恢复时间的存储装置包括同步写恢复时间控制块，其接收用于执行自动预充电操作的控制信号，并且延迟控制信号，只要与写入相对应的操作时钟的某个时钟部分 恢复时间，异步写入恢复时间控制块，用于延迟耦合到其上的控制信号，只要与写恢复时间相对应的固定延迟时间，用于选择同步写恢复时间控制块的选择块或异步写恢复时间 控制块，以及自动预充电控制块，其作为自动预充电执行信号输出，用于在执行自动预充电操作时响应于同步写入恢复时间控制块或异步写入恢复时间控制块输出的信号 写命令。

公开(公告)号：US5912899A

公开(公告)日：1999-06-15

申请号：US772696

申请日：1996-12-23

申请人： Tae-Yun Kim ,  Hyun-Sung Hwang

发明人： Tae-Yun Kim ,  Hyun-Sung Hwang

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  G11C29/34 ,  G11C29/48 ,  G01R31/28

CPC分类号： G11C7/1078 ,  G11C29/12 ,  G11C29/34 ,  G11C29/48 ,  G11C7/1006

摘要： An integrated circuit memory device includes first and second input buffers, and first and second input bus lines corresponding to the first and second input buffers. The first input buffer is connected to the first input bus line while a transfer gate is provided between the second input buffer and the second input bus line. The transfer gate connects the second input buffer with the second input bus line during a data input-output operation and disconnects the second input buffer from the second input bus line during a memory test operation. A coupling circuit couples the first and second input bus lines during the memory test operation so that a data value from the first input bus line is inverted and applied to the second input bus line responsive to a first value of an address buffer output during the memory test operation. The data value from the first input line is applied to the second input bus line without inversion responsive to a second value of the address buffer output during the memory test operation. Furthermore, a coupling circuit isolates the first and second input bus lines during the data input-output operation.

摘要翻译： 集成电路存储器件包括第一和第二输入缓冲器，以及对应于第一和第二输入缓冲器的第一和第二输入总线。 第一输入缓冲器连接到第一输入总线，同时在第二输入缓冲器和第二输入总线之间提供传输门。 在数据输入 - 输出操作期间，传输门将第二输入缓冲器与第二输入总线连接，并且在存储器测试操作期间将第二输入缓冲器与第二输入总线断开。 耦合电路在存储器测试操作期间耦合第一和第二输入总线，使得来自第一输入总线的数据值被反相并且响应于在存储器期间输出的地址缓冲器的第一值而被施加到第二输入总线 测试操作。 在存储器测试操作期间，响应于地址缓冲器输出的第二值，来自第一输入行的数据值被施加到第二输入总线，而不反转。 此外，耦合电路在数据输入 - 输出操作期间隔离第一和第二输入总线。

公开(公告)号：US09186127B2

公开(公告)日：2015-11-17

申请号：US13108427

申请日：2011-05-16

申请人： Sandstrom Kurt ,  Dae Young Kim ,  Soo Hwan Shin ,  Tae-Yun Kim

发明人： Sandstrom Kurt ,  Dae Young Kim ,  Soo Hwan Shin ,  Tae-Yun Kim

IPC分类号： A61B8/00 ,  A61B5/00 ,  A61B17/00 ,  G01S7/52

CPC分类号： A61B8/54 ,  A61B8/4444 ,  A61B8/465 ,  A61B8/467 ,  A61B8/56 ,  A61B8/585 ,  G01S7/5205

摘要： Provided is a method of controlling voltage levels of overall outputs in a combinational mode, in an ultrasonic diagnosis apparatus that may operate in the combinational mode. A judging unit of the ultrasonic diagnosis apparatus may judge whether at least a part of individual modes included in the combinational mode exceeds a threshold determined by safety standards, in accordance with an inputted overall output voltage level control command. When it is judged that at least the part of the individual modes exceeds the threshold determined by the safety standards, an output control unit may maintain an individual output with respect to the at least the part, among the voltage levels that may be outputted from a transducer, to be below the threshold, so that the individual output may be below the standards in accordance with the overall output control command.

摘要翻译： 提供了一种在组合模式中可以操作的超声波诊断装置中控制组合模式的总输出的电压电平的方法。 超声波诊断装置的判断单元可以根据输入的总输出电压电平控制指令来判断组合模式中包括的各个模式的至少一部分是否超过由安全标准确定的阈值。 当判定至少部分单个模式超过由安全标准确定的阈值时，输出控制单元可以相对于至少该部分保持可输出的电压中的至少一部分的单独输出 传感器低于阈值，使得单个输出可以根据总输出控制命令低于标准。

公开(公告)号：USD687831S1

公开(公告)日：2013-08-13

申请号：US29422779

申请日：2012-05-23

申请人： Tae-Yun Kim

设计人： Tae-Yun Kim