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    BANK BASED SELF REFRESH CONTROL APPARATUS IN SEMICONDUCTOR MEMORY DEVICE AND ITS METHOD
    1.
    发明申请
    BANK BASED SELF REFRESH CONTROL APPARATUS IN SEMICONDUCTOR MEMORY DEVICE AND ITS METHOD 有权
    半导体存储器件中的基于银行的自熔控制装置及其方法

    公开(公告)号：US20050270874A1

    公开(公告)日：2005-12-08

    申请号：US11027195

    申请日：2004-12-30

    申请人： Hwang Hur ,  Tae-Yun Kim

    发明人： Hwang Hur ,  Tae-Yun Kim

    IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C11/406

    CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622

    摘要： A partial array self refresh (PASR) control apparatus for use in a semiconductor memory device having a plurality of banks includes: a bank deselection unit having a plurality of bank deselection signal output units for receiving a plurality of PASR code signals, wherein input terminal lines of each bank deselection signal output unit and signal lines of the plurality of PASR code signals are crossed each other and are selectively coupled each other.

    摘要翻译： 一种用于具有多个存储体的半导体存储器件的部分阵列自刷新（PASR）控制装置包括：具有多个存储体取消信号输出单元的存储体取消选择单元，用于接收多个PASR编码信号，其中输入端子行 每个存储体取消选择信号输出单元和多个PASR码信号的信号线彼此交叉并且被选择性地彼此耦合。

    Delay detecting apparatus of delay element in semiconductor device and method thereof
    3.
    发明授权
    Delay detecting apparatus of delay element in semiconductor device and method thereof 失效
    半导体装置中的延迟元件的延迟检测装置及其方法

    公开(公告)号：US07493533B2

    公开(公告)日：2009-02-17

    申请号：US11017646

    申请日：2004-12-22

    申请人： Tae-Yun Kim ,  Hwang Hur ,  Jun-Gi Choi

    发明人： Tae-Yun Kim ,  Hwang Hur ,  Jun-Gi Choi

    IPC分类号： G11C29/00

    CPC分类号： G11C29/50012 ,  G11C29/02 ,  G11C2029/0403

    摘要： A delay detecting apparatus detects delay amounts of delay elements in a semiconductor device by using a test mode. The semiconductor device comprises a delay signal detecting unit for detecting delays of delay elements in the semiconductor device by using a signal that is synchronized with an external clock, and a delay signal outputting unit for outputting a delayed signal from the delay signal detecting unit to a data pad by using the signal that is synchronized with the external clock.

    摘要翻译： 延迟检测装置通过使用测试模式来检测半导体器件中的延迟元件的延迟量。 半导体器件包括延迟信号检测单元，用于通过使用与外部时钟同步的信号来检测半导体器件中的延迟元件的延迟;以及延迟信号输出单元，用于将延迟信号从延迟信号检测单元输出到 通过使用与外部时钟同步的信号进行数据传输。

    Delay detecting apparatus of delay element in semiconductor device and method thereof
    4.
    发明申请
    Delay detecting apparatus of delay element in semiconductor device and method thereof 失效
    半导体装置中的延迟元件的延迟检测装置及其方法

    公开(公告)号：US20050229051A1

    公开(公告)日：2005-10-13

    申请号：US11017646

    申请日：2004-12-22

    申请人： Tae-Yun Kim ,  Hwang Hur ,  Jun-Gi Choi

    发明人： Tae-Yun Kim ,  Hwang Hur ,  Jun-Gi Choi

    IPC分类号： G11C29/00 ,  G11C29/02

    CPC分类号： G11C29/50012 ,  G11C29/02 ,  G11C2029/0403

    摘要： A delay detecting apparatus detects delay amounts of delay elements in a semiconductor device by using a test mode. The semiconductor device comprises a delay signal detecting unit for detecting delays of delay elements in the semiconductor device by using a signal that is synchronized with an external clock, and a delay signal outputting unit for outputting a delayed signal from the delay signal detecting unit to a data pad by using the signal that is synchronized with the external clock.

    摘要翻译： 延迟检测装置通过使用测试模式来检测半导体器件中的延迟元件的延迟量。 半导体器件包括延迟信号检测单元，用于通过使用与外部时钟同步的信号来检测半导体器件中的延迟元件的延迟;以及延迟信号输出单元，用于将延迟信号从延迟信号检测单元输出到 通过使用与外部时钟同步的信号进行数据传输。

    Bank based self refresh control apparatus in semiconductor memory device and its method
    5.
    发明授权
    Bank based self refresh control apparatus in semiconductor memory device and its method 有权
    半导体存储器件中的基于银行的自刷新控制装置及其方法

    公开(公告)号：US07088635B2

    公开(公告)日：2006-08-08

    申请号：US11027195

    申请日：2004-12-30

    申请人： Hwang Hur ,  Tae-Yun Kim

    发明人： Hwang Hur ,  Tae-Yun Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622

    摘要： A partial array self refresh (PASR) control apparatus for use in a semiconductor memory device having a plurality of banks includes: a bank deselection unit having a plurality of bank deselection signal output units for receiving a plurality of PASR code signals, wherein input terminal lines of each bank deselection signal output unit and signal lines of the plurality of PASR code signals are crossed each other and are selectively coupled each other.

    摘要翻译： 一种用于具有多个存储体的半导体存储器件的部分阵列自刷新（PASR）控制装置包括：具有多个存储体取消信号输出单元的存储体取消选择单元，用于接收多个PASR编码信号，其中输入端子行 每个存储体取消选择信号输出单元和多个PASR码信号的信号线彼此交叉并且被选择性地彼此耦合。

    Method of refreshing a memory device utilizing PASR and piled refresh schemes
    6.
    发明申请
    Method of refreshing a memory device utilizing PASR and piled refresh schemes 有权
    使用PASR和堆叠刷新方案刷新存储器件的方法

    公开(公告)号：US20060104139A1

    公开(公告)日：2006-05-18

    申请号：US11125687

    申请日：2005-05-10

    申请人： Hwang Hur ,  Tae Yun Kim

    发明人： Hwang Hur ,  Tae Yun Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40611 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622

    摘要： In a memory device having an N number of banks, a refresh operation according to a piled refresh scheme is performed during a self-refresh mode to refresh the N number of banks in regular sequence when it is necessary to refresh all of the N number of banks. A refresh operation according to a Partial Array Self Refresh (PASR) scheme is performed during a self-refresh mode when it is necessary to refresh only an i number of banks (where 1

    摘要翻译： 在具有N个存储体的存储器件中，在自刷新模式期间执行根据堆叠刷新方案的刷新操作，以便在需要刷新N个数量的N个存储块时，按规则顺序刷新N个存储区 银行。 在自刷新模式期间，当仅需刷新i个存储体（其中1

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07979758B2

    公开(公告)日：2011-07-12

    申请号：US12154870

    申请日：2008-05-28

    申请人： Hwang Hur ,  Chang-Ho Do ,  Jae-Bum Ko ,  Jin-Il Chung

    发明人： Hwang Hur ,  Chang-Ho Do ,  Jae-Bum Ko ,  Jin-Il Chung

    IPC分类号： G11C29/00 ,  G01R31/28

    CPC分类号： G11C29/12 ,  G11C11/401

    摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

    摘要翻译： 半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元执行包括写入操作的多个内部操作来检测缺陷 在晶圆级别。

    Multi-port memory device
    8.
    发明授权
    Multi-port memory device 有权
    多端口存储设备

    公开(公告)号：US07835219B2

    公开(公告)日：2010-11-16

    申请号：US11647617

    申请日：2006-12-28

    申请人： Hwang Hur ,  Jae-Il Kim

    发明人： Hwang Hur ,  Jae-Il Kim

    IPC分类号： G11C8/00

    CPC分类号： G11C7/10 ,  G11C7/1048 ,  G11C7/1075

    摘要： A multi-port memory device including a plurality of ports, a plurality of banks and a plurality of bank controllers, wherein all of the bank controllers share all of the ports, the device includes a phase locked loop (PLL) unit for generating an internal clock signal; a delay unit, provided in each bank controller, for generating first and second delayed clock signals by delaying the internal clock signal; a serializer, provided in each bank controller, for receiving a plurality of parallel data from all of the ports and fitting the parallel data for a corresponding data frame in response to the first delayed clock signal; and a command decoder, provided in each bank controller, for decoding output data of the serializer to generate command signals in response to the second delayed clock signal.

    摘要翻译： 一种包括多个端口，多个存储体和多个存储体控制器的多端口存储器件，其中所有存储体控制器共享所有端口，该器件包括用于产生内部的锁相环（PLL）单元 时钟信号; 延迟单元，设置在每个存储体控制器中，用于通过延迟内部时钟信号产生第一和第二延迟的时钟信号; 设置在每个存储体控制器中的串行器，用于响应于第一延迟时钟信号从所有端口接收多个并行数据并针对对应的数据帧拟合并行数据; 以及设置在每个存储体控制器中的命令解码器，用于解码串行器的输出数据，以响应于第二延迟的时钟信号产生命令信号。

    Test circuit for multi-port memory device
    9.
    发明授权
    Test circuit for multi-port memory device 有权
    多端口存储器件测试电路

    公开(公告)号：US07808851B2

    公开(公告)日：2010-10-05

    申请号：US12474243

    申请日：2009-05-28

    申请人： Hwang Hur ,  Chang-Ho Do

    发明人： Hwang Hur ,  Chang-Ho Do

    IPC分类号： G11C29/00

    CPC分类号： G11C29/26 ,  G11C8/16 ,  G11C11/401

    摘要： A semiconductor memory device includes a read bus line for transferring read data; a write bus line for transferring write data; and a temporary data storage unit connected between the read bus line and the write bus line and controlled by a test mode signal enabled during a test mode.

    摘要翻译： 半导体存储器件包括用于传送读取数据的读出总线; 用于传送写入数据的写入总线; 以及临时数据存储单元，连接在读总线和写总线之间，并由在测试模式期间启用的测试模式信号控制。

    Multi-port memory device
    10.
    发明申请
    Multi-port memory device 有权
    多端口存储设备

    公开(公告)号：US20080077747A1

    公开(公告)日：2008-03-27

    申请号：US11647617

    申请日：2006-12-28

    申请人： Hwang Hur ,  Jae-Il Kim

    发明人： Hwang Hur ,  Jae-Il Kim

    IPC分类号： G06F13/00

    CPC分类号： G11C7/10 ,  G11C7/1048 ,  G11C7/1075

    摘要： A multi-port memory device including a plurality of ports, a plurality of banks and a plurality of bank controllers, wherein all of the bank controllers share all of the ports, the device includes a phase locked loop (PLL) unit for generating an internal clock signal; a delay unit, provided in each bank controller, for generating first and second delayed clock signals by delaying the internal clock signal; a serializer, provided in each bank controller, for receiving a plurality of parallel data from all of the ports and fitting the parallel data for a corresponding data frame in response to the first delayed clock signal; and a command decoder, provided in each bank controller, for decoding output data of the serializer to generate command signals in response to the second delayed clock signal.

    摘要翻译： 一种包括多个端口，多个存储体和多个存储体控制器的多端口存储器件，其中所有存储体控制器共享所有端口，该器件包括用于产生内部的锁相环（PLL）单元 时钟信号; 延迟单元，设置在每个存储体控制器中，用于通过延迟内部时钟信号产生第一和第二延迟的时钟信号; 设置在每个存储体控制器中的串行器，用于响应于第一延迟时钟信号从所有端口接收多个并行数据并针对对应的数据帧拟合并行数据; 以及设置在每个存储体控制器中的命令解码器，用于解码串行器的输出数据，以响应于第二延迟的时钟信号产生命令信号。