公开(公告)号：US20210406027A1

公开(公告)日：2021-12-30

申请号：US17373592

申请日：2021-07-12

Applicant: Hyperion Core, Inc.

Inventor： Martin VORBACH

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

Abstract: The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly, checking for an Execution Unit (EXU) available for receiving a new instruction, and issuing the instruction to the available Execution Unit and entering a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).

公开(公告)号：US20190079769A1

公开(公告)日：2019-03-14

申请号：US16130856

申请日：2018-09-13

Applicant: Hyperion Core, Inc.

Inventor： Martin VORBACH

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/355 ,  G06F9/32

Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

公开(公告)号：US20180039576A1

公开(公告)日：2018-02-08

申请号：US15663651

申请日：2017-07-28

Applicant: Hyperion Core, Inc.

Inventor： Martin VORBACH

IPC: G06F9/52

CPC classification number: G06F12/0815 ,  G06F9/526 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0893 ,  G06F2212/271 ,  G06F2212/50 ,  G06F2212/62 ,  Y02D10/13

Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.

公开(公告)号：US20210026637A1

公开(公告)日：2021-01-28

申请号：US17070689

申请日：2020-10-14

Applicant: Hyperion Core, Inc.

Inventor： Martin VORBACH

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32 ,  G06F9/355

Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

公开(公告)号：US20200241879A1

公开(公告)日：2020-07-30

申请号：US16560895

申请日：2019-09-04

Applicant: Hyperion Core, Inc.

Inventor： Martin VORBACH ,  Frank MAY ,  Markus WEINHARDT

IPC: G06F9/38 ,  G06F8/41 ,  G06F9/30

Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

公开(公告)号：US20170364338A1

公开(公告)日：2017-12-21

申请号：US15643554

申请日：2017-07-07

Applicant: Hyperion Core, Inc.

Inventor： Martin VORBACH

IPC: G06F9/45 ,  G06F17/50

CPC classification number: G06F9/3001 ,  G06F8/41 ,  G06F8/443 ,  G06F8/4434 ,  G06F8/447 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5054

Abstract: The present invention related to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.

公开(公告)号：US20160004639A1

公开(公告)日：2016-01-07

申请号：US14791350

申请日：2015-07-03

Applicant: Hyperion Core Inc.

Inventor： Martin VORBACH

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F9/526 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0893 ,  G06F2212/271 ,  G06F2212/50 ,  G06F2212/62 ,  Y02D10/13

Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.

Abstract translation: 本发明涉及多核处理器系统，特别是单包多核处理器系统，其包括至少两个处理器核，优选至少四个处理器核，所述至少两个核中的每一个优选地至少四个处理器 具有本地LEVEL-1缓存，组合多个LEVEL-1高速缓存的树通信结构，该树具有1个节点，优选地至少有三个节点用于四个处理器。 核心多核处理器，并且TAG信息与在树中管理的数据相关联，可用于处理数据。

公开(公告)号：US20180004530A1

公开(公告)日：2018-01-04

申请号：US15535697

申请日：2015-12-13

Applicant: Hyperion Core, Inc.

Inventor： Martin VORBACH

IPC: G06F9/38

Abstract: The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises: 1) looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly; 2) checking for an Execution Unit (EXU) available for receiving a new instruction; and 3) issuing the instruction to the available Execution Unit and enter a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).

公开(公告)号：US20160048394A1

公开(公告)日：2016-02-18

申请号：US14830704

申请日：2015-08-19

Applicant: Hyperion Core, Inc.

Inventor： Martin VORBACH ,  Frank MAY ,  Markus WEINHARDT

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/45

CPC classification number: G06F9/3836 ,  G06F8/443 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30065 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30134 ,  G06F9/30189 ,  G06F9/381 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889

Abstract: The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Abstract translation: 本发明公开了一种单芯片顺序处理器，其包括至少一个ALU块，其中所述顺序处理器能够在处理数据时保持其操作码，以克服在每个时钟周期中需要新指令的必要性。

公开(公告)号：US20240054097A1

公开(公告)日：2024-02-15

申请号：US18382974

申请日：2023-10-23

Applicant: Hyperion Core, Inc.

Inventor： Martin VORBACH

IPC: G06F15/78 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0893

CPC classification number: G06F15/7839 ,  G06F9/3017 ,  G06F9/30043 ,  G06F9/345 ,  G06F9/38 ,  G06F15/7821 ,  G06F12/0893 ,  G06F2213/0038 ,  G11C8/16

Abstract: Implementations relate to a data processor that includes a data processing unit having a plurality of processing elements and a cache hierarchy including a plurality of levels of data caches. The data caches include a first level data cache connected to a second level data cache, and a main memory connected to the highest level cache of the cache hierarchy. At least one of the first level data cache or second level data cache is divided into a plurality of cache segments, and during operation of the data processor, at least some of the plurality of cache segments are excluded from cache operation. Each of the excluded cache segments is dedicated to an associated processing element as tightly coupled local access memory.