公开(公告)号：US20130083596A1

公开(公告)日：2013-04-04

申请号：US13337200

申请日：2011-12-26

Applicant: Hyung-Min LEE

Inventor： Hyung-Min LEE

IPC: G11C16/10

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

Abstract: Embodiments of present invention relate to a nonvolatile memory device that includes a first page buffer controlling any one of a first even bit line and a first odd bit line; a second page buffer controlling any one of a second even bit line and a second odd bit line; wherein the second page buffer operates the second odd bit line according to program when the first page buffer operates the first even bit line according to program, and the second page buffer operates the second even bit line according to program when the first page buffer operates the first odd bit line according to program.

Abstract translation: 本发明的实施例涉及一种非易失性存储器件，其包括控制第一偶数位线和第一奇数位线中的任何一个的第一页缓冲器; 第二页缓冲器，其控制第二偶数位线和第二奇数位线中的任何一个; 其中当第一页缓冲器根据程序操作第一偶数位线时，第二页缓冲器根据程序操作第二奇数位线，并且当第一页缓冲器操作第二页缓冲器时，第二页缓冲器根据程序操作第二偶数位线 根据程序的第一个奇数位线。

公开(公告)号：US20130315003A1

公开(公告)日：2013-11-28

申请号：US13602952

申请日：2012-09-04

Applicant: Hyung-Min LEE

Inventor： Hyung-Min LEE

IPC: G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C16/06 ,  G11C16/24 ,  G11C16/26

Abstract: A memory includes a cell string including a plurality of memory cells connected in series, a bit line connected to the cell string, a voltage transfer unit configured to electrically connect the bit line and a sensing node in response to a control signal, and a page buffer configured to sense a voltage of the bit line through the sensing node in a sensing period, wherein the page buffer decides a voltage level of the control signal based on a threshold voltage of the target memory cell, which corresponds to a verification target among the plurality of memory cells in the sensing period.

Abstract translation: 存储器包括：单元串，包括串联连接的多个存储单元，连接到单元串的位线;电压转移单元，被配置为响应于控制信号电连接位线和感测节点;以及页面 缓冲器，其被配置为在感测周期中感测通过感测节点的位线的电压，其中，所述寻呼缓冲器基于所述目标存储器单元的阈值电压来决定所述控制信号的电压电平，所述阈值电压对应于所述目标存储器单元中的验证目标 在感测周期中的多个存储器单元。