公开(公告)号：US20080079086A1

公开(公告)日：2008-04-03

申请号：US11831069

申请日：2007-07-31

申请人： Hyung-suk Jung ,  Jong-ho Lee ,  Sung-kee Han ,  Ho Lee ,  Ha-jin Lim

发明人： Hyung-suk Jung ,  Jong-ho Lee ,  Sung-kee Han ,  Ho Lee ,  Ha-jin Lim

IPC分类号： H01L21/336 ,  H01L27/085

CPC分类号： H01L21/823807

摘要： A semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device includes a semiconductor substrate in which PMOS transistor regions and NMOS transistor regions are formed, a PMOS transistor including P-type source and drain regions and a gate electrode, and an NMOS transistor formed on an Si channel region between N-type source and drain regions. The PMOS transistor is formed in each PMOS transistor region, and the gate electrode is formed on a high-dielectric gate insulating film formed on an SiGe channel region between the P-type source and drain regions. Further, the NMOS transistor includes a high-dielectric gate insulating film and a gate electrode formed on the gate insulating film, and the NMOS transistor is formed in each NMOS transistor region.

摘要翻译： 一种半导体器件和半导体器件的制造方法，其中半导体器件包括其中形成有PMOS晶体管区域和NMOS晶体管区域的半导体衬底，包括P型源极和漏极区域的PMOS晶体管和栅极电极，以及 形成在N型源区和漏区之间的Si沟道区上的NMOS晶体管。 PMOS晶体管形成在每个PMOS晶体管区域中，并且栅电极形成在形成在P型源区和漏区之间的SiGe沟道区上的高电介质栅极绝缘膜上。 此外，NMOS晶体管包括高电介质栅极绝缘膜和形成在栅极绝缘膜上的栅电极，并且NMOS晶体管形成在每个NMOS晶体管区域中。

公开(公告)号：US07952118B2

公开(公告)日：2011-05-31

申请号：US11946153

申请日：2007-11-28

申请人： Hyung-suk Jung ,  Jong-ho Lee ,  Sung-kee Han ,  Ha-jin Lim

发明人： Hyung-suk Jung ,  Jong-ho Lee ,  Sung-kee Han ,  Ha-jin Lim

IPC分类号： H01L29/78

CPC分类号： H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/02362 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3142 ,  H01L21/31645 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： A semiconductor includes a channel region in a semiconductor substrate, a gate dielectric film on the channel region, and a gate on the gate dielectric film. The gate includes a doped metal nitride film, formed from a nitride of a first metal and doped with a second metal which is different from the first metal, and a conductive polysilicon layer formed on the doped metal nitride film. The gate may further include a metal containing capping layer interposed between the doped metal nitride film and the conductive polysilicon layer.

摘要翻译： 半导体包括半导体衬底中的沟道区域，沟道区上的栅极电介质膜和栅极电介质膜上的栅极。 栅极包括由第一金属的氮化物形成并掺杂有与第一金属不同的第二金属的掺杂金属氮化物膜和形成在掺杂金属氮化物膜上的导电多晶硅层。 栅极还可以包括插入在掺杂的金属氮化物膜和导电多晶硅层之间的含金属的覆盖层。

公开(公告)号：US20070178637A1

公开(公告)日：2007-08-02

申请号：US11699784

申请日：2007-01-30

申请人： Hyung-suk Jung ,  Cheol-kyu Lee ,  Jong-ho Lee ,  Sung-kee Han ,  Yun-seok Kim

发明人： Hyung-suk Jung ,  Cheol-kyu Lee ,  Jong-ho Lee ,  Sung-kee Han ,  Yun-seok Kim

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： A method of fabricating a gate of a semiconductor device using an oxygen-free ashing process is disclosed. The method includes forming a high-k dielectric film, having a dielectric constant higher than a silicon oxide film, on a semiconductor substrate including an NMOS region and a PMOS region, forming an etching target film on the high-k dielectric film, forming a photoresist pattern to expose any one region of the two regions, on the etching target film, etching the etching target film using the photoresist pattern as an etching mask, and removing the photoresist pattern using plasma formed in the presence of an oxygen-free reactive gas.

摘要翻译： 公开了一种使用无氧灰化工艺制造半导体器件的栅极的方法。 该方法包括在包括NMOS区域和PMOS区域的半导体衬底上形成具有高于氧化硅膜的介电常数的高k电介质膜，在高k电介质膜上形成蚀刻靶膜，形成 光致抗蚀剂图案以暴露两个区域的任何一个区域，在蚀刻目标膜上，使用光刻胶图案蚀刻蚀刻目标膜作为蚀刻掩模，以及使用在无氧反应气体存在下形成的等离子体去除光致抗蚀剂图案 。

公开(公告)号：US07323419B2

公开(公告)日：2008-01-29

申请号：US11338633

申请日：2006-01-25

申请人： Hyung-suk Jung ,  Jong-ho Lee ,  Jae-eon Park ,  Sung-kee Han ,  Min-joo Kim

发明人： Hyung-suk Jung ,  Jong-ho Lee ,  Jae-eon Park ,  Sung-kee Han ,  Min-joo Kim

IPC分类号： H01L22/302

CPC分类号： H01L29/517 ,  H01L21/02172 ,  H01L21/265 ,  H01L21/28194 ,  H01L21/31691 ,  H01L21/32134 ,  H01L21/32135

摘要： A method of fabricating a semiconductor device including a high-k dielectric for as a gate insulating layer is provided. The method includes forming a high-k dielectric layer and a conductive layer on a substrate, dry etching a portion of the conductive layer, performing a process to increase a wet etch rate of a remaining portion of the conductive layer, and forming a conductive layer pattern by wet etching the remaining portion of the conductive layer after performing the plasma process or the ion implantation. The process to increase the wet etch rate of the conductive layer including a plasma process and/or an ion implantation on the remaining portion of the conductive layer.

摘要翻译： 提供一种制造包括用作栅极绝缘层的高k电介质的半导体器件的方法。 该方法包括在衬底上形成高k电介质层和导电层，干蚀刻导电层的一部分，执行增加导电层剩余部分的湿蚀刻速率的工艺，以及形成导电层 在执行等离子体处理或离子注入之后湿式蚀刻导电层的剩余部分的图案。 包括在导电层的剩余部分上包括等离子体工艺和/或离子注入的导电层的湿蚀刻速率的方法。

公开(公告)号：US20060175289A1

公开(公告)日：2006-08-10

申请号：US11338633

申请日：2006-01-25

申请人： Hyung-suk Jung ,  Jong-ho Lee ,  Jae-eon Park ,  Sung-kee Han ,  Min-joo Kim

发明人： Hyung-suk Jung ,  Jong-ho Lee ,  Jae-eon Park ,  Sung-kee Han ,  Min-joo Kim

IPC分类号： C03C15/00 ,  H01L21/302 ,  B44C1/22 ,  C23F1/00

CPC分类号： H01L29/517 ,  H01L21/02172 ,  H01L21/265 ,  H01L21/28194 ,  H01L21/31691 ,  H01L21/32134 ,  H01L21/32135

摘要： A method of fabricating a semiconductor device including a high-k dielectric for as a gate insulating layer is provided. The method includes forming a high-k dielectric layer and a conductive layer on a substrate, dry etching a portion of the conductive layer, performing a process to increase a wet etch rate of a remaining portion of the conductive layer, and forming a conductive layer pattern by wet etching the remaining portion of the conductive layer after performing the plasma process or the ion implantation. The process to increase the wet etch rate of the conductive layer including a plasma process and/or an ion implantation on the remaining portion of the conductive layer.

摘要翻译： 提供一种制造包括用作栅极绝缘层的高k电介质的半导体器件的方法。 该方法包括在衬底上形成高k电介质层和导电层，干蚀刻导电层的一部分，执行增加导电层剩余部分的湿蚀刻速率的工艺，以及形成导电层 在执行等离子体处理或离子注入之后湿式蚀刻导电层的剩余部分的图案。 包括在导电层的剩余部分上包括等离子体工艺和/或离子注入的导电层的湿蚀刻速率的方法。

公开(公告)号：US09508727B2

公开(公告)日：2016-11-29

申请号：US14853442

申请日：2015-09-14

申请人： Hong-bae Park ,  Ja-hum Ku ,  Myeong-cheol Kim ,  Jin-wook Lee ,  Sung-kee Han

发明人： Hong-bae Park ,  Ja-hum Ku ,  Myeong-cheol Kim ,  Jin-wook Lee ,  Sung-kee Han

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L27/02

CPC分类号： H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

摘要： A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

摘要翻译： 一种方法包括在衬底上提供多个有源区，以及在所述多个有源区中的两个之间的至少第一器件隔离层，其中所述多个有源区在第一方向上延伸; 提供沿第二方向延伸的栅极层，所述栅极层形成多条栅极线，所述栅极线包括相对于彼此以直线延伸的第一栅极线和第二栅极线，所述第二栅极线和第二栅极线之间具有间隔，所述第一栅极 线和第二栅极线交叉有效区域中的至少一个，提供覆盖第一器件隔离层并围绕第一和第二栅极线周围的有源区域覆盖的绝缘层; 以及在所述第一栅极线和所述第二栅极线之间的空间中提供栅极间绝缘区域。