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    Method of manufacturing a semiconductor memory device
    1.
    发明授权
    Method of manufacturing a semiconductor memory device 有权
    制造半导体存储器件的方法

    公开(公告)号：US07402488B2

    公开(公告)日：2008-07-22

    申请号：US11159130

    申请日：2005-06-23

    申请人： Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

    发明人： Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L27/10852 ,  H01L28/91

    摘要： A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.

    摘要翻译： 半导体存储器件的制造方法包括在半导体衬底上形成含碳层，在含碳层上形成绝缘层图案，将含碳层的上表面部分地露出的绝缘层图案， 蚀刻含碳层的暴露部分，形成用于限定存储节点孔的含碳层图案，在存储节点孔内部形成底部电极，在存储节点孔内部的底部电极上形成电介质层， 所述介电层覆盖所述底部电极，并且在所述存储节点孔内部的所述电介质层上形成上部电极，所述上部电极覆盖所述电介质层。

    Surface wave coupled plasma etching apparatus
    3.
    发明授权
    Surface wave coupled plasma etching apparatus 失效
    表面波耦合等离子体蚀刻装置

    公开(公告)号：US06228210B1

    公开(公告)日：2001-05-08

    申请号：US09295629

    申请日：1999-04-20

    申请人： Cheol-kyu Lee

    发明人： Cheol-kyu Lee

    IPC分类号： H05H100

    CPC分类号： H01J37/32192

    摘要： A surface wave coupled plasma etching apparatus according to the present invention can produce a plasma within a confined area above an etching object by a microwave confinement plate, so as to prevent an upper portion of the apparatus from being sputtered by the plasma. The microwave confinement plate is interposed between a pair of glass plates, so that the microwave confinement plate is not exposed to and sputtered by the plasma during an etching process. The lower glass plate which protects the microwave confinement plate from the plasma is formed so as not to change a temperature of itself rapidly when the etching stops, and thereby an undesirable polymer adhesion to the lower glass plate is avoided.

    摘要翻译： 根据本发明的表面波耦合等离子体蚀刻装置可以通过微波限制板在蚀刻对象之上的限制区域内产生等离子体，以防止装置的上部被等离子体溅射。 微波限制板介于一对玻璃板之间，使得微波限制板在蚀刻过程中不被等离子体暴露并溅射。 形成保护微波限制板与等离子体的下部玻璃板，以便在蚀刻停止时不使其自身温度快速变化，从而避免了对下部玻璃板的不良聚合物的粘附。

    Semiconductor memory device and method of forming the same
    4.
    发明申请
    Semiconductor memory device and method of forming the same 有权
    半导体存储器件及其形成方法

    公开(公告)号：US20090026515A1

    公开(公告)日：2009-01-29

    申请号：US12219358

    申请日：2008-07-21

    申请人： Kyoung-Sub Shin ,  Cheol-Kyu Lee ,  Sung-il Cho ,  Young-Kyu Cho

    发明人： Kyoung-Sub Shin ,  Cheol-Kyu Lee ,  Sung-il Cho ,  Young-Kyu Cho

    IPC分类号： H01L29/94 ,  H01L21/4763

    CPC分类号： H01L28/91 ,  H01L27/10855 ,  H01L27/10888

    摘要： Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad.

    摘要翻译： 示例性实施例涉及半导体存储器件和形成半导体存储器件的方法。 半导体存储器件可以包括半导体衬底上的第一层间绝缘层。 位线可以在第一层间绝缘层上沿第一方向布置。 位线接触焊盘可以设置在第一层间绝缘层中并且电连接到位线。 存储接触焊盘可以设置在第一层间绝缘层中。 位线接触焊盘的顶表面可以低于存储触点焊盘的顶表面。

    Method of fabricating gate of semiconductor device using oxygen-free ashing process
    5.
    发明申请
    Method of fabricating gate of semiconductor device using oxygen-free ashing process 审中-公开
    使用无氧灰化工艺制造半导体器件栅极的方法

    公开(公告)号：US20070178637A1

    公开(公告)日：2007-08-02

    申请号：US11699784

    申请日：2007-01-30

    申请人： Hyung-suk Jung ,  Cheol-kyu Lee ,  Jong-ho Lee ,  Sung-kee Han ,  Yun-seok Kim

    发明人： Hyung-suk Jung ,  Cheol-kyu Lee ,  Jong-ho Lee ,  Sung-kee Han ,  Yun-seok Kim

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823842

    摘要： A method of fabricating a gate of a semiconductor device using an oxygen-free ashing process is disclosed. The method includes forming a high-k dielectric film, having a dielectric constant higher than a silicon oxide film, on a semiconductor substrate including an NMOS region and a PMOS region, forming an etching target film on the high-k dielectric film, forming a photoresist pattern to expose any one region of the two regions, on the etching target film, etching the etching target film using the photoresist pattern as an etching mask, and removing the photoresist pattern using plasma formed in the presence of an oxygen-free reactive gas.

    摘要翻译： 公开了一种使用无氧灰化工艺制造半导体器件的栅极的方法。 该方法包括在包括NMOS区域和PMOS区域的半导体衬底上形成具有高于氧化硅膜的介电常数的高k电介质膜，在高k电介质膜上形成蚀刻靶膜，形成 光致抗蚀剂图案以暴露两个区域的任何一个区域，在蚀刻目标膜上，使用光刻胶图案蚀刻蚀刻目标膜作为蚀刻掩模，以及使用在无氧反应气体存在下形成的等离子体去除光致抗蚀剂图案 。

    Method of optimizing seasoning recipe for etch process
    6.
    发明申请
    Method of optimizing seasoning recipe for etch process 审中-公开

    公开(公告)号：US20060293781A1

    公开(公告)日：2006-12-28

    申请号：US11510987

    申请日：2006-08-28

    申请人： Hong Cho ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee ,  Hye-Jin Jo

    发明人： Hong Cho ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee ,  Hye-Jin Jo

    IPC分类号： G06F19/00

    CPC分类号： H01L21/67253 ,  H01L21/32137 ,  H01L21/67069 ,  H01L22/20

    摘要： A method for optimizing a seasoning recipe for a dry etch process. The method includes setting a critical value of reproducibility, a main etch recipe, and a preliminary seasoning recipe. A test wafer is then etched using the preliminary seasoning recipe in a dry etch chamber. Next, a main etch process is performed with respect to at least 10 run wafers in the dry etch chamber using the main etch recipe and an end-point detection time for each wafer is determined. An initial dispersion and a standard deviation are then determined using the determined end-point detection times. The critical value of reproducibility is then compared to the initial dispersion. If the initial dispersion is equal to or less than the critical value of reproducibility, the preliminary seasoning recipe is used as the seasoning recipe, otherwise the preliminary seasoning recipe is modified and the process is repeated until an optimal seasoning recipe is determined.

    Method of optimizing seasoning recipe for etch process
    7.
    发明授权
    Method of optimizing seasoning recipe for etch process 失效
    优化蚀刻工艺调味配方的方法

    公开(公告)号：US07118926B2

    公开(公告)日：2006-10-10

    申请号：US10652403

    申请日：2003-08-29

    申请人： Hong Cho ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee ,  Hye-Jin Jo

    发明人： Hong Cho ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee ,  Hye-Jin Jo

    IPC分类号： H01L21/00

    CPC分类号： H01L21/67253 ,  H01L21/32137 ,  H01L21/67069 ,  H01L22/20

    摘要： A method for optimizing a seasoning recipe for a dry etch process. The method includes setting a critical value of reproducibility, a main etch recipe, and a preliminary seasoning recipe. A test wafer is then etched using the preliminary seasoning recipe in a dry etch chamber. Next, a main etch process is performed with respect to at least 10 run wafers in the dry etch chamber using the main etch recipe and an end-point detection time for each wafer is determined. An initial dispersion and a standard deviation are then determined using the determined end-point detection times. The critical value of reproducibility is then compared to the initial dispersion. If the initial dispersion is equal to or less than the critical value of reproducibility, the preliminary seasoning recipe is used as the seasoning recipe, otherwise the preliminary seasoning recipe is modified and the process is repeated until an optimal seasoning recipe is determined.

    摘要翻译： 一种优化干蚀刻工艺调味配方的方法。 该方法包括设置重现性的临界值，主蚀刻配方和初步调味配方。 然后使用干蚀刻室中的初步调味配方蚀刻测试晶片。 接下来，使用主蚀刻配方对干蚀刻室中的至少10个运行晶片执行主蚀刻处理，并且确定每个晶片的终点检测时间。 然后使用确定的终点检测时间确定初始色散和标准偏差。 然后将重现性的临界值与初始色散进行比较。 如果初始分散度等于或小于再现性的临界值，则使用初步调味配方作为调味配方，否则初步调味配方被修改，重复该过程直到确定最佳调味配方。

    Method of forming fine pattern of semiconductor device using SiGe layer as sacrificial layer, and method of forming self-aligned contacts using the same
    8.
    发明申请
    Method of forming fine pattern of semiconductor device using SiGe layer as sacrificial layer, and method of forming self-aligned contacts using the same 有权
    使用SiGe层作为牺牲层形成精细图案的半导体器件的方法以及使用其形成自对准触点的方法

    公开(公告)号：US20050282363A1

    公开(公告)日：2005-12-22

    申请号：US11157435

    申请日：2005-06-21

    申请人： Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

    发明人： Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

    IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/36 ,  H01L21/469 ,  H01L21/60

    CPC分类号： H01L21/0331 ,  H01L21/0332 ,  H01L21/76897

    摘要： There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.

    摘要翻译： 提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。 形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，并且形成硅锗（Si 1-Si） xTi）x牺牲层，其具有等于或高于至少导电线结构的高度的高度，在基底的整个表面上。 然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。 使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。 然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。

    Method of etching material film formed on semiconductor wafer using surface wave coupled plasma etching apparatus
    9.
    发明授权
    Method of etching material film formed on semiconductor wafer using surface wave coupled plasma etching apparatus 失效
    使用表面波耦合等离子体蚀刻装置在半导体晶片上形成的材料膜的蚀刻方法

    公开(公告)号：US06479390B1

    公开(公告)日：2002-11-12

    申请号：US09556733

    申请日：2000-04-21

    申请人： Cheol-kyu Lee

    发明人： Cheol-kyu Lee

    IPC分类号： H01L21302

    CPC分类号： H01J37/32192 ,  H01L21/31116

    摘要： A method of etching a material film formed on a semiconductor wafer loaded onto a reaction chamber of a surface wave coupled plasma etching apparatus having an insulation plate which is capable of generating surface waves by microwaves, and a glass plate placed below the insulation plate, for transmitting the produced surface waves. In the method, the glass plate is rapidly pre-heated by generating an argon (Ar) or xenon (Xe) surface wave coupled plasma which has a high ion density and a large mass, and the material layer is then etched. Therefore, the preheating time of the glass plate can be sharply reduced to less than five minutes. Also, because the etching gas is not used for the heating of the glass, damage to the glass plate can be reduced and generation of polymer on the glass plate is suppressed with an improved etching efficiency, so that failure in etching can also be avoided.

    摘要翻译： 一种蚀刻形成在装载到能够通过微波产生表面波的绝缘板的表面波耦合等离子体蚀刻装置的反应室上的半导体晶片上形成的材料膜的方法和放置在绝缘板下方的玻璃板， 传输产生的表面波。 在该方法中，通过产生具有高离子密度和大质量的氩（Ar）或氙（Xe）表面波耦合等离子体来快速预热玻璃板，然后蚀刻该材料层。 因此，玻璃板的预热时间可以急剧减少到5分钟以下。 此外，由于蚀刻气体不用于玻璃的加热，因此可以降低玻璃板的损伤，并且以提高的蚀刻效率抑制玻璃板上的聚合物的产生，从而也可以避免蚀刻失败。

    Semiconductor memory device and method of forming the same
    10.
    发明授权
    Semiconductor memory device and method of forming the same 有权
    半导体存储器件及其形成方法

    公开(公告)号：US07728375B2

    公开(公告)日：2010-06-01

    申请号：US12219358

    申请日：2008-07-21

    申请人： Kyoung-Sub Shin ,  Cheol-Kyu Lee ,  Sung-il Cho ,  Young-Kyu Cho

    发明人： Kyoung-Sub Shin ,  Cheol-Kyu Lee ,  Sung-il Cho ,  Young-Kyu Cho

    IPC分类号： H01L27/108

    CPC分类号： H01L28/91 ,  H01L27/10855 ,  H01L27/10888

    摘要： Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad.

    摘要翻译： 示例性实施例涉及半导体存储器件和形成半导体存储器件的方法。 半导体存储器件可以包括半导体衬底上的第一层间绝缘层。 位线可以在第一层间绝缘层上沿第一方向布置。 位线接触焊盘可以设置在第一层间绝缘层中并电连接到位线。 存储接触焊盘可以设置在第一层间绝缘层中。 位线接触焊盘的顶表面可以低于存储触点焊盘的顶表面。