公开(公告)号：US3893071A

公开(公告)日：1975-07-01

申请号：US49851074

申请日：1974-08-19

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  HSIAO MU-YUE ,  PATEL ARVIN M

IPC: G06F12/16 ,  G06F11/10 ,  H04L1/10 ,  G11C29/00

CPC classification number: G06F11/1028

Abstract: This specification describes an error correction system for a high density memory made up of a number of monolithic wafers each containing a plurality of arrays that are addressed thru circuitry and wiring contained on that wafer. The storage bits on the wafers are functionally divided into a number of blocks each containing a plurality of words. The words of each block are on several wafers with each word made up of a plurality of arrays on a single array wafer. Each word in a block is protected by a similar error correction double multiple error detection code. The block is further protected by two additional check words made up using a b-adjacent code. Each byte in the check words protects one byte position of the words of the block. When a single error is detected in any word by the SEC-MED code the code corrects the error. If a multiple error is detected, the multiple error signal points to the word in error to be corrected by the b-adjacent code check words.

Abstract translation: 本说明书描述了用于由多个单片晶片组成的高密度存储器的纠错系统，每个单片晶片包含通过电路和包含在该晶片上的布线来寻址的多个阵列。 晶片上的存储位在功能上被划分为多个块，每个块包含多个单词。 每个块的单词在几个晶片上，每个单词由单个阵列晶片上的多个阵列组成。 块中的每个字都受到类似的纠错双重错误检测码的保护。 该块进一步受到使用b相邻代码组成的两个附加检查词的保护。 检查字中的每个字节保护块的字的一个字节位置。 当SEC-MED代码在任何单词中检测到单个错误时，代码将纠正错误。 如果检测到多重错误，则多个错误信号指向错误的单词，以便通过b相邻的代码检查字进行纠正。

公开(公告)号：US3601798A

公开(公告)日：1971-08-24

申请号：US3601798D

申请日：1970-02-03

Applicant: IBM

Inventor： HSIAO MU-YUE

IPC: H03M13/19 ,  G06F11/08 ,  G08C25/00

CPC classification number: H03M13/19 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057

Abstract: A single error correcting system for correcting messages of any number of data bits comprises encoding means and decoding means. The encoding means adds r check bits, each check bit representative of at most r-1 data bits and, on the average, each check bit representative of >r/2 data bits; each check bit is representative of no more than one common data bit; and each data bit is represented by exactly two check bits. The decoding means for each data bit has an error correcting circuit receiving three inputs from input circuitry, one input being the data bit itself and the other two inputs being combinations, respectively, of one of the two check bits and other data bits representative of the received data bit. The error correcting circuit is capable of producing an output correctly corresponding to the data bit if no more than one input thereto was in error. A double error detecting system, useful with this single error correcting system, inputs syndrome bits representative of each check bit and of an added parity bit to an OR circuit and to an ADDER circuit, and compares the output from these circuits.

公开(公告)号：US3893070A

公开(公告)日：1975-07-01

申请号：US43153074

申请日：1974-01-07

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  CORDI VINCENT A ,  HSIAO MU-YUE ,  SHIFFRIN BARRY N ,  GLICK ELLIS W

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H04L1/10

CPC classification number: G06F11/1048

Abstract: An error correction and detection circuit includes a modular encoder that provides the minimum number of check bits for encoding a particular number of data bits. Means is provided for combining several units to produce the minimum number of code bits when a larger data word is to be encoded. A storage hierarchy system using this error correction circuit is also disclosed.

Abstract translation: 纠错和检测电路包括一个模块化编码器，其提供用于编码特定数量的数据位的最小数量的校验位。 提供了用于组合几个单元以在要编码较大数据字时产生最小数量的码位的装置。 还公开了一种使用该纠错电路的存储层级系统。

公开(公告)号：US3623155A

公开(公告)日：1971-11-23

申请号：US3623155D

申请日：1969-12-24

Applicant: IBM

Inventor： HSIAO MU-YUE ,  KOLANKOWSKY EUGENE

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/19

CPC classification number: H03M13/19

Abstract: Errors in code words transmitted over a communication path are detected and corrected by optimum apparatus at transmitting and receiving ends of the path. Illustratively, a 72 bit parallel code word, comprising a 64 bit information portion and an eight bit check portion is communicated between a transmitter and a receiver. A check bit generator at the transmitter generates eight check bits as a function of the 64 information bits, each check bit being associated with a number of information bits (a check bit and its associated information bits forming a ''''code group''''). The information bits and check bits are communicated to the receiver where an error detector compares check bits generated from the received information bits with the received check bits and an error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The check bit generator at the transmitter supplies signals, at outputs corresponding to the check bits, by Exclusive ORing the information bits in its code group, in accordance with a single error correction and double error detection (SEC/DED) code. The error detector examines each code group separately by Exclusive ORing both its information and check bits in accordance with the same code and supplies syndrome signals manifesting the result of the examination. Error detection and correction are possible because, upon transmission, each code group contains an even number of bits (even parity), only one of which is a check bit, and each bit of each code word is a member of an odd number of code groups. At the receiver, a single correctable error is assumed to have occurred if an odd number of received code groups contains an odd number of bits (odd parity) and an uncorrectable double error is assumed to have occurred if an even number of code groups have odd parity. Single errors are then located and corrected as an AND function of the odd parity code groups. The check bit generator, error detector and error locator are designed in accordance with a technique for using a minimum number of components and a uniform number of components in each parallel signal path. Among the design goals are: each unique code group should substantially contain the same number of bits, each information bit must be a member of an odd number of code groups greater than one, and each check bit must be a member of a different code group. The number of code groups to which each information bit is assigned is determined by first exhausting the lowest odd number of code group combinations available before going to the next odd number of combinations.

公开(公告)号：US3656107A

公开(公告)日：1972-04-11

申请号：US3656107D

申请日：1970-10-23

Applicant: IBM

Inventor： HSIAO MU-YUE ,  MIKHAIL WADIE F

IPC: H03M13/13 ,  G08C25/00

CPC classification number: H03M13/13

Abstract: A method and apparatus are provided for detecting and correcting double errors automatically by generating syndrome S bits from a binary word having check bits and data bits. The syndrome S bits themselves are decoded to locate and correct single errors. Wen double errors occur in the binary word, the syndrome S bits automatically operate a switching device which changes the bits of the binary word one at a time to correct one of the double errors. If one of the double errors is not corrected when a given bit is changed, this is indicated by the syndrome S bits, and the bit under test is restored as the next bit of the binary word is changed or complemented. Whenever one of the double errors is corrected by the switching device, the syndrome bits then indicate the location of the remaining single error, and the syndrome S bits are decoded to correct the second one of the double errors.

Abstract translation: 提供了一种通过从具有校验位和数据位的二进制字中产生校正子S位来自动检测和校正双重误差的方法和装置。 综合征S位本身被解码以定位和纠正单个错误。 文双字错误出现在二进制字中，综合征S位自动操作一个切换装置，它一次更改一个二进制字的位，以纠正一个双重错误。 当给定位改变时，如果双精度错误中的一个未被纠正，则由校验位S位指示，并且当二进制字的下一位被改变或补充时，被测位被恢复。 无论何时一个双重错误由开关装置校正，则校正子位然后指示剩余的单个错误的位置，并且校正子S位被解码以校正第二个双重错误。

公开(公告)号：US3452328A

公开(公告)日：1969-06-24

申请号：US3452328D

申请日：1965-06-07

Applicant: IBM

Inventor： HSIAO MU-YUE ,  SIH KWANG Y

IPC: H04L1/00 ,  G08B29/00 ,  G08B25/00

CPC classification number: H04L1/0057

公开(公告)号：US5552591B1

公开(公告)日：2000-05-02

申请号：US2129893

申请日：1993-02-22

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  CHEN CHIN-LONG ,  DILL FREDERICK H ,  GOODMAN DOUGLAS S ,  HSIAO MU-YUE ,  MCCANN PAUL V ,  MULLIGAN JAMES M ,  RAND RICKY A

IPC: G06K1/12 ,  G06K7/016 ,  G06K7/10 ,  G06K19/06

CPC classification number: G06K7/10861 ,  G06K1/126 ,  G06K7/0166 ,  G06K19/06028 ,  G06K2019/06253

公开(公告)号：US3876978A

公开(公告)日：1975-04-08

申请号：US36693673

申请日：1973-06-04

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  HSIAO MU-YUE ,  PATEL ARVIND M

IPC: G06F12/16 ,  G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  G11B27/36 ,  G06K5/02

CPC classification number: G06F11/1076 ,  G06F11/1008

Abstract: This specification describes a system for preventing the catastrophic loss of data in one storage unit of a storage system comprised of a plurality of such storage units. In this system one of the plurality of storage units is used to store parity bits for the storage system, bit position by bit position. To be more specific, if the data in each of the storage units is considered to be a linear string of bits the storage unit containing the parity bits would contain a parity or Exclusive OR sum of all the first bits of all the storage units or, in a more general case, the j.sup.th bit of the check storage unit is the parity or Exclusive OR sum of all the j bits of all the storage units.

公开(公告)号：US3582878A

公开(公告)日：1971-06-01

申请号：US3582878D

申请日：1969-01-08

Applicant: IBM ,  ROBERT T CHIEN

Inventor： BOSSEN DOUGLAS C ,  CHIEN ROBERT T ,  HSIAO MU-YUE ,  SELLERS FREDERICK F JR

IPC: H03M13/19 ,  H04L1/00 ,  H04L1/10 ,  G08C25/00

CPC classification number: H04L1/0057 ,  H03M13/19 ,  H04L1/0041

Abstract: The error correcting system is capable of correcting multiple random errors in data messages of k m2 data bits where m is an integer. The message is encoded by adding 2m check bits for each additional error correcting capability. The encoded message after data transfer and storage is decoded by parity checking and threshold logic decision circuits. The parity checking circuits are constructed in modular form. Each additional module adds a further error correcting capability. The outputs from each module form inputs to the threshold logic decision circuit where the error correction is made. Detection of an additional error can be simply achieved by an overall parity circuit.