公开(公告)号：US3623155A

公开(公告)日：1971-11-23

申请号：US3623155D

申请日：1969-12-24

Applicant: IBM

Inventor： HSIAO MU-YUE ,  KOLANKOWSKY EUGENE

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/19

CPC classification number: H03M13/19

Abstract: Errors in code words transmitted over a communication path are detected and corrected by optimum apparatus at transmitting and receiving ends of the path. Illustratively, a 72 bit parallel code word, comprising a 64 bit information portion and an eight bit check portion is communicated between a transmitter and a receiver. A check bit generator at the transmitter generates eight check bits as a function of the 64 information bits, each check bit being associated with a number of information bits (a check bit and its associated information bits forming a ''''code group''''). The information bits and check bits are communicated to the receiver where an error detector compares check bits generated from the received information bits with the received check bits and an error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The check bit generator at the transmitter supplies signals, at outputs corresponding to the check bits, by Exclusive ORing the information bits in its code group, in accordance with a single error correction and double error detection (SEC/DED) code. The error detector examines each code group separately by Exclusive ORing both its information and check bits in accordance with the same code and supplies syndrome signals manifesting the result of the examination. Error detection and correction are possible because, upon transmission, each code group contains an even number of bits (even parity), only one of which is a check bit, and each bit of each code word is a member of an odd number of code groups. At the receiver, a single correctable error is assumed to have occurred if an odd number of received code groups contains an odd number of bits (odd parity) and an uncorrectable double error is assumed to have occurred if an even number of code groups have odd parity. Single errors are then located and corrected as an AND function of the odd parity code groups. The check bit generator, error detector and error locator are designed in accordance with a technique for using a minimum number of components and a uniform number of components in each parallel signal path. Among the design goals are: each unique code group should substantially contain the same number of bits, each information bit must be a member of an odd number of code groups greater than one, and each check bit must be a member of a different code group. The number of code groups to which each information bit is assigned is determined by first exhausting the lowest odd number of code group combinations available before going to the next odd number of combinations.

公开(公告)号：US3643236A

公开(公告)日：1972-02-15

申请号：US3643236D

申请日：1969-12-19

Applicant: IBM

Inventor： KOLANKOWSKY EUGENE ,  MCMAHON ROBERT F ,  PERLMAN DAVID J

IPC: G11C8/16 ,  G11C15/00

CPC classification number: G11C8/16

Abstract: In a storage array wherein several locations are simultaneously accessed, each location includes a circuit settable to one of two conditions by signals on lines defining its position. Defining the storage position by three lines, ''''horizontal,'''' ''''vertical'''' and ''''diagonal,'''' each circuit may be selected by activating its diagonal line and either the horizontal or vertical line for that circuit. The storage cell is a solid-stage flip-flop with two cross-coupled active devices and additional active device for each of the three driving lines. Connections to each circuit through selected ones of the vertical and horizontal lines communicate information on the inactivated line.

Abstract translation: 在其中几个位置被同时访问的存储阵列中，每个位置包括通过定义其位置的线上的信号可设置为两个状态之一的电路。 可以通过激活其对角线以及该电路的水平线或垂直线来将每个电路定义为“水平”，“垂直”和“对角线”三行的存储位置。 存储单元是具有两个交叉耦合有源器件的固体触发器和用于三个驱动线中的每一个的附加有源器件。 通过所选择的垂直和水平线路连接到每个电路，在灭活的线路上传送信息。

公开(公告)号：US3638204A

公开(公告)日：1972-01-25

申请号：US3638204D

申请日：1969-12-19

Applicant: IBM

Inventor： KOLANKOWSKY EUGENE

IPC: G11C8/16 ,  G11C11/40 ,  H03K3/286

CPC classification number: G11C8/16

Abstract: A storage cell especially suited for use in an array of cells wherein cells may be simultaneously accessed by a plurality of different addressing systems for reading and writing of information via independent sensing and bit driving devices. A latch, constructed from field effect transistors (FET) in a known manner, is selected for accessing by driver lines, retaining and indicating information in accordance with signals supplied on a sense bit driver line pair. The number of drivers required to select the cell and the number of sense bit driver line pairs are increased by providing additional FET devices to gate, in accordance with selected driver signals, information between the latch and sense bit driver line pairs selected in accordance with the relative locations of information simultaneously accessed in the array.

Abstract translation: 特别适合用于单元阵列的存储单元，其中单元可以被多个不同寻址系统同时访问，用于通过独立的感测和位驱动装置读取和写入信息。 选择以已知方式由场效应晶体管（FET）构成的锁存器，用于通过驱动器线访问，根据在感测位驱动器线对上提供的信号保留和指示信息。 根据所选择的驱动器信号，通过根据所选择的驱动器信号在根据所选择的驱动器信号选择的锁存器和感测位驱动器线对之间的信息来向栅极提供额外的FET器件来增加选择单元所需的驱动器数量和感测位驱动器线对数量 在阵列中同时访问的信息的相对位置。

公开(公告)号：US3638199A

公开(公告)日：1972-01-25

申请号：US3638199D

申请日：1969-12-19

Applicant: IBM

Inventor： KOLANKOWSKY EUGENE ,  MCMAHON ROBERT F

IPC: G11C11/41 ,  G11C7/00 ,  G11C11/06 ,  G06F1/00

CPC classification number: G11C11/06035

Abstract: In a data-processing system, a central processing unit and a group of input/output units simultaneously read information from, and write information into, several locations of a single storage unit. The storage is provided with two storage address registers and two data registers. Each storage address register specifies a location in storage with which information in the associated data register is communicated. The storage is an array of storage elements each of which is selected by driving two out of three wires associated with that storage element. Characterizing the three wires as X, Y and Z, each location is accessed by driving the Z-wire for that location and one of the X- or Y-wires. A magnetic core, capable of assuming one of two states in accordance with half select information on two of three wires threaded through it, is disclosed as an example of a storage element. Sense amplifiers, connected to the X- and Y-wires, receive stored information from the undriven wire.

Abstract translation: 在数据处理系统中，中央处理单元和一组输入/输出单元同时从单个存储单元的多个位置读取信息并向其写入信息。 存储器具有两个存储地址寄存器和两个数据寄存器。 每个存储地址寄存器指定在存储器中与相关联的数据寄存器中的信息通信的位置。 存储器是存储元件的阵列，每个存储元件通过驱动与该存储元件相关联的三条线中的两条来选择。 将三条线表征为X，Y和Z，通过驱动该位置的Z线和X线或Y线中的一条来访问每个位置。 作为存储元件的示例，公开了一种能够根据穿过其中的三根电线上的两根上的半选择信息来假设两种状态之一的磁芯。 连接到X和Y线的感应放大器从未驱动的电线接收存储的信息。

公开(公告)号：US3573728A

公开(公告)日：1971-04-06

申请号：US3573728D

申请日：1969-01-09

Applicant: IBM

Inventor： KOLANKOWSKY EUGENE ,  PATTIN AUGUST K JR

IPC: G06F11/10 ,  H04L1/10 ,  H04B3/46

CPC classification number: G06F11/1056

Abstract: This invention provides coding circuits for storing words in a memory in an error correction code and for operating with an associated system in which data is provided with error detecting parity check bits. The coding circuits include means for locating an incorrect bit of a memory word and for updating the error correction bits to correspond to the corrected word.