公开(公告)号：US3629824A

公开(公告)日：1971-12-21

申请号：US3629824D

申请日：1970-02-12

Applicant: IBM

Inventor： BOSSEN DOUGLAS C

IPC: H03M13/13 ,  H04L1/00 ,  G06F11/12 ,  G08C25/00

CPC classification number: H04L1/0057 ,  H03M13/13

Abstract: WHEREIN I is the identity element and A1, A2,...AK are distinct nonzero elements of Galois Field (2b), wherein the indicated multiplication and addition are the Galois Field defined operations, and wherein b is an integer > 1, and K is an integer 2
Apparatus including an encoder adapted for encoding blocks of data into a sent message and a decoder adapted for recovering the data from a received message corresponding to the sent message but which may be in error wherein the blocks of data consist of K-bytes of data (D1, D2,...DK) each of b bits. The sent message comprises the K-bytes of data plus two check bytes C1 and C2, each of b bits. The decoder is effective in recovering the data without error when not more than a single byte of the received message is in error no matter how many bits may be in error in the single byte. The encoder computes the check bytes according to the relationships

公开(公告)号：US3893071A

公开(公告)日：1975-07-01

申请号：US49851074

申请日：1974-08-19

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  HSIAO MU-YUE ,  PATEL ARVIN M

IPC: G06F12/16 ,  G06F11/10 ,  H04L1/10 ,  G11C29/00

CPC classification number: G06F11/1028

Abstract: This specification describes an error correction system for a high density memory made up of a number of monolithic wafers each containing a plurality of arrays that are addressed thru circuitry and wiring contained on that wafer. The storage bits on the wafers are functionally divided into a number of blocks each containing a plurality of words. The words of each block are on several wafers with each word made up of a plurality of arrays on a single array wafer. Each word in a block is protected by a similar error correction double multiple error detection code. The block is further protected by two additional check words made up using a b-adjacent code. Each byte in the check words protects one byte position of the words of the block. When a single error is detected in any word by the SEC-MED code the code corrects the error. If a multiple error is detected, the multiple error signal points to the word in error to be corrected by the b-adjacent code check words.

Abstract translation: 本说明书描述了用于由多个单片晶片组成的高密度存储器的纠错系统，每个单片晶片包含通过电路和包含在该晶片上的布线来寻址的多个阵列。 晶片上的存储位在功能上被划分为多个块，每个块包含多个单词。 每个块的单词在几个晶片上，每个单词由单个阵列晶片上的多个阵列组成。 块中的每个字都受到类似的纠错双重错误检测码的保护。 该块进一步受到使用b相邻代码组成的两个附加检查词的保护。 检查字中的每个字节保护块的字的一个字节位置。 当SEC-MED代码在任何单词中检测到单个错误时，代码将纠正错误。 如果检测到多重错误，则多个错误信号指向错误的单词，以便通过b相邻的代码检查字进行纠正。

公开(公告)号：US3697948A

公开(公告)日：1972-10-10

申请号：US3697948D

申请日：1970-12-18

Applicant: IBM

Inventor： BOSSEN DOUGLAS C

IPC: G11B20/18 ,  H04L1/00 ,  G06F11/00

CPC classification number: H04L1/0057 ,  G11B20/1833 ,  H03M13/1575 ,  H03M13/159

Abstract: Apparatus including a decoder adapted for recovering the data from a received message corresponding to the sent message but which may be in error wherein the blocks of data consist of k bytes of data (D0, D1, D2,...Dk 1) each of b bits. The sent message comprises the k bytes of data plus two check bytes C1 and C2, each of b bits. The decoder is effective in recovering the data without error when not more than two of the bytes are in error no matter how many bits may be in error in the two bytes. Pointers are required which indicate the two bytes containing errors. In the absence of the pointers or in the presence of a single false pointer, the decoder is effective in recovering the data without error when not more than a single byte is in error no matter how many bits may be in error in the single byte. The message is encoded by computing the check bytes according to the relationship: C1 ID0 + ID1 +...+ IDk 1 C2 ID0 + T D1 + T2 D2 +...+ Tk 1 Dk 1 WHEREIN I is the identity element and T, T2,...,Tk 1 are distinct non-zero elements of Galois Field (2b) wherein the indicated multiplication and addition are the Galois Field defined operations, and wherein b is an integer > 1 and k is an integer 2

Abstract translation: 包括解码器的装置，其适于从对应于所发送的消息的接收消息中恢复数据，但是可能是错误的，其中数据块由每个数据（D0，D1，D2，... Dk-1）的k字节组成 的b位。 发送的消息包括k个字节的数据加上两个校验字节C1和C2，每个b位。 无论两个字节中有多少位可能出现错误，解码器在不超过两个字节有错误的情况下无误地恢复数据。 需要指示指示包含错误的两个字节的指针。 在没有指针或存在单个错误指针的情况下，无论单个字节中有多少位可能出现错误，解码器在不超过单个字节有错误的情况下无效地恢复数据是有效的。 消息通过根据以下关系计算检查字节进行编码：

公开(公告)号：US3893070A

公开(公告)日：1975-07-01

申请号：US43153074

申请日：1974-01-07

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  CORDI VINCENT A ,  HSIAO MU-YUE ,  SHIFFRIN BARRY N ,  GLICK ELLIS W

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H04L1/10

CPC classification number: G06F11/1048

Abstract: An error correction and detection circuit includes a modular encoder that provides the minimum number of check bits for encoding a particular number of data bits. Means is provided for combining several units to produce the minimum number of code bits when a larger data word is to be encoded. A storage hierarchy system using this error correction circuit is also disclosed.

Abstract translation: 纠错和检测电路包括一个模块化编码器，其提供用于编码特定数量的数据位的最小数量的校验位。 提供了用于组合几个单元以在要编码较大数据字时产生最小数量的码位的装置。 还公开了一种使用该纠错电路的存储层级系统。

公开(公告)号：US3671947A

公开(公告)日：1972-06-20

申请号：US3671947D

申请日：1970-09-28

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  HSIAO MUYUE

IPC: G06F11/10 ,  H03M13/15 ,  G08C25/00 ,  G06F11/12

CPC classification number: G06F11/1012 ,  H03M13/15

Abstract: In apparatus for correcting an error in a codeword according to a syndrome, means is provided for transforming the computed syndrome through a succession of syndrome sequences or values and for counting the number of syndrome sequences in the succession. The values of each syndrome sequence are sensed to detect a distinct predetermined value and the bit in error is located from the count of the number of syndrome sequences and inverted for correction. The preferred embodiment uses a shortened BoseChaudhuri codeword and uses a linear feedback shift register to transform the syndrome values.

Abstract translation: 在用于根据综合征校正码字中的错误的装置中，提供了用于通过连续的综合征序列或值对所计算的综合征进行变换并用于计数继代中的综合征序列的数量的装置。 感测每个校正子序列的值以检测不同的预定值，并且错误位位于校正子序列数的计数并反转以进行校正。 优选实施例使用缩短的Bose-Chaudhuri码字，并使用线性反馈移位寄存器来变换校正子值。

公开(公告)号：US5552591B1

公开(公告)日：2000-05-02

申请号：US2129893

申请日：1993-02-22

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  CHEN CHIN-LONG ,  DILL FREDERICK H ,  GOODMAN DOUGLAS S ,  HSIAO MU-YUE ,  MCCANN PAUL V ,  MULLIGAN JAMES M ,  RAND RICKY A

IPC: G06K1/12 ,  G06K7/016 ,  G06K7/10 ,  G06K19/06

CPC classification number: G06K7/10861 ,  G06K1/126 ,  G06K7/0166 ,  G06K19/06028 ,  G06K2019/06253

公开(公告)号：US3876978A

公开(公告)日：1975-04-08

申请号：US36693673

申请日：1973-06-04

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  HSIAO MU-YUE ,  PATEL ARVIND M

IPC: G06F12/16 ,  G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  G11B27/36 ,  G06K5/02

CPC classification number: G06F11/1076 ,  G06F11/1008

Abstract: This specification describes a system for preventing the catastrophic loss of data in one storage unit of a storage system comprised of a plurality of such storage units. In this system one of the plurality of storage units is used to store parity bits for the storage system, bit position by bit position. To be more specific, if the data in each of the storage units is considered to be a linear string of bits the storage unit containing the parity bits would contain a parity or Exclusive OR sum of all the first bits of all the storage units or, in a more general case, the j.sup.th bit of the check storage unit is the parity or Exclusive OR sum of all the j bits of all the storage units.

公开(公告)号：US3675200A

公开(公告)日：1972-07-04

申请号：US3675200D

申请日：1970-11-23

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  HENLE ROBERT A ,  HSIAO MU Y ,  MALEY GERALD A ,  PRICER W DAVID

IPC: G06F11/10 ,  G11C29/00 ,  G06F11/08 ,  G06K5/00

CPC classification number: G06F11/1008 ,  G06F11/1076 ,  G11C29/003

Abstract: Errors in parallel binary data produced by a plurality of data track, e.g., a plurality of parallel shift registers, are corrected by a system in which the shift registers which are stuck, i.e., inalterable, are determined and counted. By single Hamming error detection means, the presence of a Hamming error and an indication of the bit position of a single Hamming error is made. Comparison means determine if the indicated Hamming error is coincident with a stuck track. Then, dependent on the parity condition of the data as well as the count of stuck tracks, apparatus is provided for complementing one or more of the stuck tracks and/or correcting the indicated Hamming error.

Abstract translation: 由多个数据磁道（例如多个并行移位寄存器）产生的并行二进制数据的错误由其中确定并计数被卡住的，即不可更改的移位寄存器的系统来校正。 通过单个汉明误差检测装置，进行汉明误差的存在和单个汉明误差的比特位置的指示。 比较装置确定所指示的汉明误差是否与卡盘轨迹一致。 然后，依赖于数据的奇偶校验条件以及卡盘轨迹的计数，提供装置用于补充一个或多个卡住轨迹和/或校正所指示的汉明误差。

公开(公告)号：US3634821A

公开(公告)日：1972-01-11

申请号：US3634821D

申请日：1970-04-13

Applicant: IBM

Inventor： BOSSEN DOUGLAS C

IPC: H03M13/43 ,  G08C25/00

CPC classification number: H03M13/43 ,  H04L1/0041 ,  H04L1/0057

Abstract: A multiple error correcting system for correcting t (t 2) errors in message of k data bits, m2 k (m+1)2, where m is an integer of at least three, comprises encoding means and decoding means. The encoding means adds r check bits, each check bit corresponding to a number of data bits; each data bit is represented by 2t check bits; these 2t check bits have only the one data bit in common; and, the number, r, of check bits is: 2mt r 2(m+1)t. The decoding means for each data bit has an error correcting circuit receiving 2t+1 inputs from input circuitry, the inputs being the data bit itself, and 2t combinations of check bits and other data bits representing the data bit. The error correcting circuit is capable of producing an output signal correctly corresponding to a data bit if no more than t inputs thereto for that data bit were in error. A coding system for generating these r check bits by augmenting Latin square codes is described.

Abstract translation: 用于校正k个数据位的消息中的t（t 2）错误的多重纠错系统，m2 k（m + 1）2，其中m是至少为3的整数，包括编码装置和解码装置。 编码装置加上r个校验位，每个校验位对应于多个数据位; 每个数据位由2t校验位表示; 这些2t校验位只有一个数据位相同; 并且，校验位的数目r为：2mt r 2（m + 1）t。 每个数据位的解码装置具有从输入电路接收2t + 1个输入的错误校正电路，输入是数据位本身，以及校验位和表示数据位的其它数据位的2t组合。 误差校正电路能够产生正确对应于数据位的输出信号，如果该数据位不超过t个输入，则该数据位是错误的。 描述了通过增加拉丁方数生成这些r校验位的编码系统。

公开(公告)号：US3582878A

公开(公告)日：1971-06-01

申请号：US3582878D

申请日：1969-01-08

Applicant: IBM ,  ROBERT T CHIEN

Inventor： BOSSEN DOUGLAS C ,  CHIEN ROBERT T ,  HSIAO MU-YUE ,  SELLERS FREDERICK F JR

IPC: H03M13/19 ,  H04L1/00 ,  H04L1/10 ,  G08C25/00

CPC classification number: H04L1/0057 ,  H03M13/19 ,  H04L1/0041

Abstract: The error correcting system is capable of correcting multiple random errors in data messages of k m2 data bits where m is an integer. The message is encoded by adding 2m check bits for each additional error correcting capability. The encoded message after data transfer and storage is decoded by parity checking and threshold logic decision circuits. The parity checking circuits are constructed in modular form. Each additional module adds a further error correcting capability. The outputs from each module form inputs to the threshold logic decision circuit where the error correction is made. Detection of an additional error can be simply achieved by an overall parity circuit.