中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.01 seconds)

    Radix conversion circuits
    4.
    发明授权
    Radix conversion circuits 失效
    RADIX转换电路

    公开(公告)号：US3700872A

    公开(公告)日：1972-10-24

    申请号：US3700872D

    申请日：1969-08-22

    Applicant: IBM

    Inventor： MAY FREDERICK T

    IPC: H03M7/08 ,  H03K13/24

    CPC classification number: H03M7/08

    Abstract: Data conversion circuits with optimized common hardware convert numbers expressed in a first radix C to other radices m1, m2, etc., with the mode of operation being controlled to establish a radix C to radix m1 conversion in one mode, a radix C to radix m2 conversion in another mode, etc., on a selective basis, as desired. In a first embodiment, numbers represented in a binary (base 2) radix C are converted to a base 10 (m1) or base 12(m2) representation. In a second embodiment, numbers stored in a ternary (base 3) radix C representation are converted to a base 12 (m1) or base 10 (m2) representation. The circuits are predicated upon recognition of the fact that a number represented in a first radix can be converted readily to a second radix using shared hardware if the following equation is satisfied:

    Abstract translation: 具有优化的通用硬件的数据转换电路将以第一基数C表示的数字转换为其他的基数m1，m2等，其中操作模式被控制以在一种模式中建立基数C至基数m1转换，基数C到基数 m2转换在另一种模式下，等等，根据需要在选择的基础上。 在第一实施例中，以二进制（基数2）基数C表示的数字被转换为基数10（m1）或基数12（m2）表示。 在第二实施例中，以三元（基数3）基数C表示形式存储的数字被转换为基数12（m1）或基数10（m2）表示。 这些电路基于以下事实的推断：如果满足以下等式，则可以使用共享硬件将第一基数表示的数字容易地转换为第二基数：m = Cn（PC + 1）m = CnX在该等式中， m表示除数，即现有数据要转换到的基数或基数。 C表示原始数据的基数或基数。 为方便起见，因子P和n是方程中使用的正整数。 如果P和n的任意值的值满足分红的指定基数C中的m的等式，则可以实现除以m。 首先确定对于任何原始源数据满足方程，以便开发适合于将源数据转换为其他基数的电路。

    Memory-centered computer system
    5.
    发明授权
    Memory-centered computer system 失效
    记忆中心计算机系统

    公开(公告)号：US3599186A

    公开(公告)日：1971-08-10

    申请号：US3599186D

    申请日：1970-05-14

    Applicant: IBM

    Inventor： MAY FREDERICK T ,  WILLIAMS THOMAS H

    IPC: G06F9/35 ,  G06F9/16

    CPC classification number: G06F9/35

    Abstract: The invention concerns a computer system with the usual input and output devices, arithmetic facilities, clocking facilities, associated control logic and incorporating memory facilities, such as a core memory, arranged in a centralized manner with respect to the other facilities of the system, and having uniquely arranged instruction and data accessing control circuitry for establishing a more efficient utilization of hardware. Basically, the core memory is arranged in a conventional manner as far as reading, writing, and transferring of data is concerned, but beyond this, has particular addressable areas designated Special Addresses for facilitating the processing of both instructions and data with a minimum amount of external hardware. The system operates with only a single address register for accessing both instruction and operand information. In a usual case, an operand is accessed and placed in the special address section of memory by using the addressing facilities. Thereafter, another operand is accessed and the operation required is performed with one operand in the special address section accessed by implied addressing, rather than accessing by the conventional addressing facilities. The foregoing arrangement requires a somewhat longer processing interval, but permits the satisfactory accomplishment of all processing required by the use of a unitary essentially single addressing facility. The system is considered to be memory-centered since the memory is involved in practically all of the operations performed in the system. Thus, for example, the memory is used in storage of data and instructions, contains index registers and input/output data address, input/output length counts, editing formats, command key conditions, and various special words required during processing of information. The system operates according to predetermined clocking intervals during which the accessing of instructions, data, input/output transfers, etc. are performed, and in connection with the memory-centered aspect of the system, the clocking circuits are arranged for permutation in order that only a single operand or a pair of operands may be accessed, as circumstances may require. The system incorporates various counting means associated with the aforementioned primary addressing facilities to control the reading and writing of information both directly, sequentially, and sequentially within a selected block of information. The latter is particularly advantageous in operations requiring a repetitive accessing of selected areas of memory, such as during certain arithmetic operations, recomplementing, Multiply operations, and so on.

Patent Agency Ranking