公开(公告)号：US3680054A

公开(公告)日：1972-07-25

申请号：US3680054D

申请日：1970-07-06

Applicant: IBM

Inventor： BUNKER WILLIAM H ,  KERR JOHN W ,  MITROFANOFF NICHOLAS S ,  SWEARINGEN KENT W

IPC: G06F13/12 ,  G06F13/34 ,  G06F9/18

CPC classification number: G06F13/122 ,  G06F13/34

Abstract: The invention relates to a unique input/output channel used in a data processing system. The channel couples a plurality of external devices and their control units to a central processing unit. The configuration of the channel is such that it allows each of the control units direct control over many of the central processing unit functions during an input/output cycle. It allows each of the control units to share the system''s main storage and central processing unit during these cycles. The design further allows for local store registers located in the central processing unit to be used as address registers for the external devices.

Abstract translation: 本发明涉及在数据处理系统中使用的独特的输入/输出通道。 信道将多个外部设备及其控制单元耦合到中央处理单元。 通道的配置使得它允许每个控制单元在输入/输出周期期间直接控制许多中央处理单元功能。 它允许每个控制单元在这些周期期间共享系统的主存储和中央处理单元。 该设计还允许位于中央处理单元中的本地存储寄存器用作外部设备的地址寄存器。

公开(公告)号：US3676852A

公开(公告)日：1972-07-11

申请号：US3676852D

申请日：1970-07-20

Applicant: IBM

Inventor： ABERNATHY ROGER E ,  MITROFANOFF NICHOLAS S

IPC: G06F9/46 ,  G06F9/18

CPC classification number: G06F9/462

Abstract: A programmed data processor having addressable core storage, a central processing unit having one or more I/O devices connected with it, two sets of program control registers-one for each of two program levels, and a switching mechanism for operating the central processing unit in two different program levels.

Abstract translation: 具有可寻址核心存储器的编程数据处理器，具有与其连接的一个或多个I / O设备的中央处理单元，两组程序控制寄存器 - 一个用于两个程序级别中的每一个，以及用于操作中央处理单元 在两个不同的程序级别。

公开(公告)号：US3596074A

公开(公告)日：1971-07-27

申请号：US3596074D

申请日：1969-06-12

Applicant: IBM

Inventor： MITROFANOFF NICHOLAS S

IPC: G06F7/00 ,  G06F7/493 ,  G06F7/495 ,  G06F7/50 ,  G06F7/506 ,  G06F11/10

CPC classification number: G06F7/495 ,  G06F11/10

Abstract: An arithmetic and logic unit consisting of a plurality of interconnected logic modules, each module operating as a subtracter in a manner that one operand is base data and the other is a modifier and controlled to perform the functions of Binary Add and Subtract, Decimal Add and Subtract, Logical AND and OR, Exclusive OR, Set Bits On-Off, Test Bits On-Off, and passing either operand (Move Operand One, Move Operand Two).

公开(公告)号：US3701105A

公开(公告)日：1972-10-24

申请号：US3701105D

申请日：1970-07-24

Applicant: IBM

Inventor： FINNEGAN EDWARD D ,  HARPER LEONARD ROY ,  MITROFANOFF NICHOLAS S ,  SLUTMAN ALLEN C

IPC: G06F15/78 ,  G06F7/00

CPC classification number: G06F15/7839

Abstract: A central processing unit which includes an arithmetic and logic unit, local store registers and general registers, allows for the use of the arithmetic and logic unit for housekeeping purposes such as address modification during portions of a machine cycle. The processing unit contains no counters or compare circuits other than the single arithmetic and logic unit with all data flow being through the arithmetic and logic unit.

Abstract translation: 包括算术和逻辑单元，本地存储寄存器和通用寄存器的中央处理单元允许使用算术和逻辑单元进行内务处理，例如在机器周期的部分期间的地址修改。 处理单元不包含单个算术和逻辑单元以外的计数器或比较电路，所有数据流都通过算术和逻辑单元。