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1.发明授权A process for fabricating semiconductor devices having compensated barrier zones between np-junctions 失效用于制备具有NP结之间的补偿障碍区的半导体器件的工艺
公开(公告)号：US3617398A
公开(公告)日：1971-11-02
申请号：US3617398D
申请日：1968-10-22
Applicant: IBM
Inventor： BILOUS OREST , MEULEMANS DARRELL R , PECORADO RAYMOND P , SELBY MICHAEL C
CPC classification number: H01L27/0821 , H01L21/00 , H01L27/0652 , Y10S148/049 , Y10S148/062 , Y10S148/085 , Y10S438/919
Abstract: A process for forming semiconductor devices by forming in a semiconductor substrate of one conductivity type a diffused region of a second conductivity type circumscribed by an adjacent gold compensated intrinsic region.
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