公开(公告)号：US10424579B2

公开(公告)日：2019-09-24

申请号：US15857022

申请日：2017-12-28

Applicant: IMEC vzw

Inventor： Mirko Scholz ,  Shih-Hung Chen

IPC: H01L29/08 ,  H01L27/02 ,  H01L29/10 ,  H02H9/04 ,  H01L29/735

Abstract: A semiconductor device for electric discharge protection is disclosed. In one aspect, the semiconductor device includes a substrate having a p-type doping. The semiconductor device includes a first well and a second well having an n-type doping and arranged spaced apart within a surface layer of the substrate, and a third well having a p-type doping and arranged in the surface layer of the substrate between the first well and the second well. The semiconductor device further includes an emitter region and a base contact region having a p-type doping and arranged within a surface layer of the first well, and a collector region having a p-type doping. The collector region is arranged at least partly within a surface layer of the third well and such that it overlaps both of the first well and the second well. An integrated circuit including a semiconductor device is also provided.

公开(公告)号：US09847336B2

公开(公告)日：2017-12-19

申请号：US15245671

申请日：2016-08-24

Applicant: IMEC VZW

Inventor： Geert Hellings ,  Geert Van der Plas ,  Mirko Scholz

IPC: H01L27/092 ,  H01L21/266 ,  H01L27/06 ,  H01L21/033 ,  H01L29/808 ,  H01L29/66 ,  H01L21/265 ,  H01L21/761 ,  H01L29/10 ,  H01L29/45 ,  H01L29/861

CPC classification number: H01L27/0928 ,  H01L21/0332 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L27/0629 ,  H01L27/098 ,  H01L29/1058 ,  H01L29/456 ,  H01L29/66128 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8611

Abstract: The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer. The method further includes, after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the gate, and forming metal contacts in the contact openings.

公开(公告)号：US20190206855A1

公开(公告)日：2019-07-04

申请号：US15857022

申请日：2017-12-28

Applicant: IMEC vzw

Inventor： Mirko Scholz ,  Shih-Hung Chen

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/735 ,  H02H9/04

CPC classification number: H01L27/0262 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/1095 ,  H01L29/735 ,  H02H9/046

Abstract: A semiconductor device for electric discharge protection is disclosed. In one aspect, the semiconductor device includes a substrate having a p-type doping. The semiconductor device includes a first well and a second well having an n-type doping and arranged spaced apart within a surface layer of the substrate, and a third well having a p-type doping and arranged in the surface layer of the substrate between the first well and the second well. The semiconductor device further includes an emitter region and a base contact region having a p-type doping and arranged within a surface layer of the first well, and a collector region having a p-type doping. The collector region is arranged at least partly within a surface layer of the third well and such that it overlaps both of the first well and the second well. An integrated circuit including a semiconductor device is also provided.

公开(公告)号：US20170062431A1

公开(公告)日：2017-03-02

申请号：US15245671

申请日：2016-08-24

Applicant: IMEC VZW

Inventor： Geert Hellings ,  Geert Van der Plas ,  Mirko Scholz

IPC: H01L27/092 ,  H01L21/266 ,  H01L27/06 ,  H01L21/033 ,  H01L29/808 ,  H01L29/66

CPC classification number: H01L27/0928 ,  H01L21/0332 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L27/0629 ,  H01L27/098 ,  H01L29/1058 ,  H01L29/456 ,  H01L29/66128 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8611

Abstract: The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer. The method further includes, after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the gate, and forming metal contacts in the contact openings.

Abstract translation: 所公开的技术涉及半导体，更具体地涉及结型场效应晶体管（JFET）。 一方面，一种制造JFET的方法包括在衬底中形成第一掺杂剂阱，其中阱通过第二掺杂剂类型的隔离区与衬底隔离。 该方法另外包括在阱的表面处注入第二掺杂剂类型的掺杂剂以形成JFET的源极，漏极和沟道，以及在阱的表面处注入第一掺杂剂类型的掺杂剂，以形成 JFET栅极。 该方法还包括在植入第一类型的掺杂剂和第二类型的掺杂剂之前，在阱上形成预金属电介质（PMD）层并在源上形成PMD层中的接触开口，漏极和 大门。 PMD层的厚度使得通过PMD层注入第一类掺杂剂和第二类掺杂剂形成沟道。 该方法还包括在注入第一类型的掺杂剂和第二类型的掺杂剂之后，将源极，漏极和栅极硅化，并在接触开口中形成金属接触。

公开(公告)号：US09263401B2

公开(公告)日：2016-02-16

申请号：US14066545

申请日：2013-10-29

Applicant: IMEC

Inventor： Geert Hellings ,  Mirko Scholz ,  Dimitri Linten

IPC: H01L23/60 ,  H01L29/36 ,  H01L29/66 ,  H01L29/866 ,  H01L29/73 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L23/60 ,  H01L27/0255 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/6609 ,  H01L29/66098 ,  H01L29/66106 ,  H01L29/66234 ,  H01L29/7302 ,  H01L29/735 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosed technology relates to a semiconductor device comprising a diode junction between two semiconductor regions of different doping types. In one aspect, the diode comprises a junction formed between an upper portion of an active area and a remainder of the active area, where the active area is defined in a substrate between two field dielectric regions. The upper portion is a portion of the active area that has a width smaller than a width of the active area itself. In another aspect, the semiconductor device is an electrostatic discharge protection device (ESD) comprising such a diode. In addition, the active area has a doping profile that exhibits a maximum value at the surface of the active area, and changes to a minimum value at a first depth, where the first depth can be greater in value than half of a depth of the upper portion. In another aspect, a method of fabrication the device does not require a separate ESD implant for lowering the holding voltage and can allow for a reduction in the number of processing steps as well as other devices comprising a diode junction.

Abstract translation: 所公开的技术涉及包括不同掺杂类型的两个半导体区域之间的二极管结的半导体器件。 在一个方面，二极管包括在有源区的上部和有源区的其余部分之间形成的结，其中有源区限定在两个场介电区之间的衬底中。 上部是活动区域的宽度小于有效区域本身的宽度的部分。 在另一方面，半导体器件是包括这种二极管的静电放电保护器件（ESD）。 此外，有源区具有在有源区的表面处呈现最大值的掺杂分布，并且在第一深度处变化为最小值，其中第一深度可以比值的深度的一半更大 上部。 在另一方面，制造该器件的方法不需要用于降低保持电压的单独的ESD注入，并且可以允许减少处理步骤的数量以及包括二极管结的其它器件。

公开(公告)号：US20140124894A1

公开(公告)日：2014-05-08

申请号：US14066545

申请日：2013-10-29

Applicant: IMEC

Inventor： Geert Hellings ,  Mirko Scholz ,  Dimitri Linten

IPC: H01L23/60 ,  H01L29/66 ,  H01L29/73

CPC classification number: H01L23/60 ,  H01L27/0255 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/6609 ,  H01L29/66098 ,  H01L29/66106 ,  H01L29/66234 ,  H01L29/7302 ,  H01L29/735 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosed technology relates to a semiconductor device comprising a diode junction between two semiconductor regions of different doping types. In one aspect, the diode comprises a junction formed between an upper portion of an active area and a remainder of the active area, where the active area is defined in a substrate between two field dielectric regions. The upper portion is a portion of the active area that has a width smaller than a width of the active area itself. In another aspect, the semiconductor device is an electrostatic discharge protection device (ESD) comprising such a diode. In addition, the active area has a doping profile that exhibits a maximum value at the surface of the active area, and changes to a minimum value at a first depth, where the first depth can be greater in value than half of a depth of the upper portion. In another aspect, a method of fabrication the device does not require a separate ESD implant for lowering the holding voltage and can allow for a reduction in the number of processing steps as well as other devices comprising a diode junction.

Abstract translation: 所公开的技术涉及包括不同掺杂类型的两个半导体区域之间的二极管结的半导体器件。 在一个方面，二极管包括在有源区的上部和有源区的其余部分之间形成的结，其中有源区限定在两个场介电区之间的衬底中。 上部是活动区域的宽度小于有效区域本身的宽度的部分。 在另一方面，半导体器件是包括这种二极管的静电放电保护器件（ESD）。 此外，有源区具有在有源区的表面处呈现最大值的掺杂分布，并且在第一深度处变化为最小值，其中第一深度可以比值的深度的一半更大 上部。 在另一方面，制造该器件的方法不需要用于降低保持电压的单独的ESD注入，并且可以允许减少处理步骤的数量以及包括二极管结的其它器件。