公开(公告)号：US20240212763A1

公开(公告)日：2024-06-27

申请号：US18392161

申请日：2023-12-21

Applicant: IMEC VZW

Inventor： Jonas Doevenspeck ,  Maarten Rosmeulen ,  Stefan Cosemans

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102

Abstract: Example embodiments relate to matrix-vector multiplications based on charge-summing memory cell strings. An example in-memory compute device for performing analog multiply-and-accumulate operations on a set of data inputs and a set of weight inputs includes a string of serially connected memory cells formed over a semiconductor channel structure, a source junction controllably connectible to one end of the string of memory cells via a string select switch, a readout circuit including a sense node controllably connectible to one end of the string of memory cells via a charge transfer switch, and control circuitry. The control circuitry is configured to apply pass mode signals, data input signals, and stop signals sequentially according to each memory cell's position along a string. The control circuitry is also configured to enable the string select switch and the charge transfer switch.