中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.013 seconds)

    WRITE-READ CIRCUIT WITH A BIT LINE MULTIPLEXER FOR A MEMORY DEVICE
    1.
    发明公开
    WRITE-READ CIRCUIT WITH A BIT LINE MULTIPLEXER FOR A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240170034A1

    公开(公告)日：2024-05-23

    申请号：US18514100

    申请日：2023-11-20

    Applicant: IMEC VZW

    Inventor： Mohit Gupta ,  Stefan Cosemans

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/1655 ,  G11C11/1673

    Abstract: A memory device with multiplexers for multiplexing write and read operations to bit lines is provided. In one aspect, a write-read circuit includes a multiplexer for multiplexing the write and read operations. The multiplexer includes a plurality of select devices, each select device being associated with one of a plurality of bit lines, and each select device including a first transistor and a second transistor. The write-read circuit further includes a controller configured to, for a write operation using a particular bit line, control the multiplexer to turn on both transistors of the first select device associated with the particular bit line, and for a read operation using the particular bit line, control the multiplexer to turn on the first transistor and turn off the second transistor of the first select device associated with the particular bit line.

    STORAGE DEVICE USING A TAPE FOR STORING DATA
    2.
    发明申请
    STORAGE DEVICE USING A TAPE FOR STORING DATA 有权

    公开(公告)号：US20210174832A1

    公开(公告)日：2021-06-10

    申请号：US17116895

    申请日：2020-12-09

    Applicant: IMEC vzw

    Inventor： Stefan Cosemans

    IPC: G11B15/26 ,  G11B5/008 ,  G11B15/60

    Abstract: A storage device including a tape configured to store data is disclosed. The tape includes a plurality of first regions with a first dielectric constant and a plurality of second regions with a second dielectric constant that is higher than the first dielectric constant. The first regions and the second regions are arranged in an alternating manner along the length of the tape. Further, the storage device includes one or more actuators configured to apply an electrical field across the width of the tape, in order to move the tape in length direction. Further, the storage device includes one or more data heads configured to read and/or write data from and/or to the tape.

    Method for manufacturing a magnetic tunnel junction device and device manufactured using such method
    3.
    发明授权
    Method for manufacturing a magnetic tunnel junction device and device manufactured using such method 有权

    公开(公告)号：US11004898B2

    公开(公告)日：2021-05-11

    申请号：US16236051

    申请日：2018-12-28

    Applicant: IMEC vzw

    Inventor： Gouri Sankar Kar ,  Stefan Cosemans

    IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

    Abstract: A magnetic tunnel junction memory device is disclosed. In one aspect, the memory device comprises a substrate, a first memory element, and a second memory element, wherein the first memory element and the second memory element are formed of a stack comprising at least a first layer and a second layer, the first layer being arranged between the substrate and the second layer. The memory device further comprises a first selector device arranged to contact the first memory element, and a second selector device arranged to contact the second memory element, wherein the first selector device and the second selector device are arranged in or above the second layer. The first memory element and the second memory element are interconnected via the first layer, and are separated from each other by a trench formed in the second layer.

    NANO-ELECTRO-MECHANICAL BASED MEMORY
    4.
    发明申请
    NANO-ELECTRO-MECHANICAL BASED MEMORY 有权
    基于纳米电子机械的存储器

    公开(公告)号：US20150179246A1

    公开(公告)日：2015-06-25

    申请号：US14558523

    申请日：2014-12-02

    Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

    Inventor： Stefan Cosemans ,  Ann Witvrouw ,  Maliheh Ramezani

    IPC: G11C11/40 ,  G11C5/06

    CPC classification number: G11C11/40 ,  G11C5/06 ,  G11C11/50 ,  G11C11/52 ,  G11C23/00

    Abstract: A non-volatile memory arrangement comprising a plurality of cells is disclosed. In one aspect, each cell comprises a memory element and a read selector in series. Further, the memory element is a nano-electro-mechanical switch comprising an anchor, a beam fixed to the anchor, a first and second control gate, for controlling the position of the beam, a first output node against which the beam can be positioned. The cell also comprises a read selector comprising a first selector terminal, a second selector terminal, the first selector terminal connected to the first output node. The first respectively second control gates of switches of a same word are connected together by a first respectively second write word line serving as control gate.

    Abstract translation: 公开了包括多个单元的非易失性存储器装置。 在一个方面，每个单元包括串联的存储元件和读选择器。 此外，存储元件是纳米机电开关，其包括锚固件，固定到锚固器的梁，用于控制梁的位置的第一和第二控制栅极，梁可以定位的第一输出节点 。 单元还包括读选择器，包括第一选择器端子，第二选择器端子，连接到第一输出节点的第一选择器端子。 相同字的开关的第一个第二控制栅极通过用作控制栅极的第一分别为第二写入字线连接在一起。

    ANALOG IN-MEMORY COMPUTING BASED INFERENCE ACCELERATOR
    5.
    发明申请
    ANALOG IN-MEMORY COMPUTING BASED INFERENCE ACCELERATOR 有权

    公开(公告)号：US20220076737A1

    公开(公告)日：2022-03-10

    申请号：US17447131

    申请日：2021-09-08

    Applicant: IMEC vzw

    Inventor： Stefan Cosemans ,  Ioannis Papistas ,  Peter Debacker

    IPC: G11C11/4096 ,  G11C11/4094 ,  G11C11/4074 ,  H03K7/08 ,  G06F17/16 ,  G06N20/00

    Abstract: A compute cell for in-memory multiplication of a digital data input and a balanced ternary weight, and an in-memory computing device including an array of the compute cells, are provided. In one aspect, the compute cell includes a set of input connectors for receiving modulated input signals representative of a sign and a magnitude of the data input, and a memory unit configured to store the ternary weight. A logic unit connected to the set of input connectors and the memory unit receives the data input and the ternary weight. The logic unit selectively enables one of a plurality of conductive paths for supplying a partial charge to a read bit line during a compound duty cycle of the set of input signals as a function of the respective signs of data input and ternary weight, and disables each of the plurality of conductive paths if at least one of the ternary weight and data input have zero magnitude.

    Non-volatile memory array using electromechanical switches for cell storage
    6.
    发明授权
    Non-volatile memory array using electromechanical switches for cell storage 有权

    公开(公告)号：US09911504B2

    公开(公告)日：2018-03-06

    申请号：US14558505

    申请日：2014-12-02

    Applicant: IMEC vzw

    Inventor： Stefan Cosemans

    IPC: G11C23/00 ,  G11C11/54 ,  H01H1/00

    CPC classification number: G11C23/00 ,  G11C11/54 ,  H01H1/0094

    Abstract: A data storage cell for storing data is disclosed. In one aspect, the data storage cell comprises a first nano electromechanical switch comprising a first moveable beam fixed to a first anchor, a first control gate and a second control gate, a first output node against which the first moveable beam can be positioned. The data storage cell also comprises a second nano electromechanical switch comprising a second moveable beam fixed to a second anchor, a third control gate and a fourth control gate. The second moveable beam can be positioned against the first output node. Further, the first nano electromechanical switch and the second nano electromechanical switch are configured for selecting a first or a second state of the data storage cell and are configured for having their moveable beam complementary positioned to the first output node. A memory arrangement of such data storage cells is also disclosed, as well as methods for writing data to the data storage cells and for reading data from the data storage cells.

    Matrix-Vector Multiplications Based on Charge-Summing Memory Cell Strings
    7.
    发明公开
    Matrix-Vector Multiplications Based on Charge-Summing Memory Cell Strings 审中-公开

    公开(公告)号：US20240212763A1

    公开(公告)日：2024-06-27

    申请号：US18392161

    申请日：2023-12-21

    Applicant: IMEC VZW

    Inventor： Jonas Doevenspeck ,  Maarten Rosmeulen ,  Stefan Cosemans

    IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

    CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102

    Abstract: Example embodiments relate to matrix-vector multiplications based on charge-summing memory cell strings. An example in-memory compute device for performing analog multiply-and-accumulate operations on a set of data inputs and a set of weight inputs includes a string of serially connected memory cells formed over a semiconductor channel structure, a source junction controllably connectible to one end of the string of memory cells via a string select switch, a readout circuit including a sense node controllably connectible to one end of the string of memory cells via a charge transfer switch, and control circuitry. The control circuitry is configured to apply pass mode signals, data input signals, and stop signals sequentially according to each memory cell's position along a string. The control circuitry is also configured to enable the string select switch and the charge transfer switch.

    METHOD FOR MANUFACTURING A MAGNETIC TUNNEL JUNCTION DEVICE AND DEVICE MANUFACTURED USING SUCH METHOD
    8.
    发明申请
    METHOD FOR MANUFACTURING A MAGNETIC TUNNEL JUNCTION DEVICE AND DEVICE MANUFACTURED USING SUCH METHOD 审中-公开

    公开(公告)号：US20190221608A1

    公开(公告)日：2019-07-18

    申请号：US16236051

    申请日：2018-12-28

    Applicant: IMEC vzw

    Inventor： Gouri Sankar Kar ,  Stefan Cosemans

    IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

    CPC classification number: H01L27/228 ,  H01L43/02 ,  H01L43/12

    Abstract: A magnetic tunnel junction memory device is disclosed. In one aspect, the memory device comprises a substrate, a first memory element, and a second memory element, wherein the first memory element and the second memory element are formed of a stack comprising at least a first layer and a second layer, the first layer being arranged between the substrate and the second layer. The memory device further comprises a first selector device arranged to contact the first memory element, and a second selector device arranged to contact the second memory element, wherein the first selector device and the second selector device are arranged in or above the second layer. The first memory element and the second memory element are interconnected via the first layer, and are separated from each other by a trench formed in the second layer.

Patent Agency Ranking