公开(公告)号：US20250048690A1

公开(公告)日：2025-02-06

申请号：US18715354

申请日：2021-12-02

Applicant: IMEC VZW ,  Huawei Technologies Co., Ltd.

Inventor： Bilal CHEHAB ,  Krishna Kumar BHUWALKA ,  Julien RYCKAERT

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: The disclosure relates to a CFET device (100) comprising: a bottom FET device (130) and a top FET device (140) stacked on top of the bottom FET device (130), the bottom FET device (130) comprising a bottom channel nanostructure (132) and a bottom gate electrode (134) comprising a side gate portion (134a) arranged along a first side surface (132a) of the bottom channel nano structure, and the top FET device (140) comprising a top channel nanosheet (142) and a top gate electrode (144) configured to define a tri-gate with respect to the top channel nanosheet and comprising a side gate portion (144b) arranged along a second side surface (142b) of the top channel nanosheet, wherein the side gate portion (134a) of the bottom gate electrode (134) defines a via contact portion protruding outside the top gate electrode (144) and the first side surface (142a) of the top channel nanosheet (142); and atop gate contact via (146) for coupling the top gate electrode (144) to a first conductive line (124) over the top FET device (140) and a bottom gate contact via (136) for coupling the via contact portion (134a) of the bottom gate electrode (134) to a second conductive line (128) over the top FET device (140).

公开(公告)号：US20220199809A1

公开(公告)日：2022-06-23

申请号：US17550383

申请日：2021-12-14

Applicant: IMEC VZW

Inventor： Julien RYCKAERT ,  Naoto HORIGUCHI ,  Boon Teik CHAN

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8234

Abstract: According to an aspect there is provided a FET device. The FET device comprises a common source body portion and a set of source layer prongs protruding therefrom in a first lateral direction. First dielectric layer portions are arranged in spaces between the source layer prongs. The device further comprises a common drain body portion and a set of drain layer prongs protruding in the first lateral direction. Second dielectric layer portions are arranged in spaces between the drain layer prongs. The device further comprises a gate body comprising a common gate body portion and a set of gate prongs protruding therefrom in a second lateral direction opposite the first lateral direction. Each gate prong is formed intermediate a respective pair of first and second dielectric layer portions. The device further comprises a channel region comprising a set of channel layer portions. Each channel layer portion extends between a respective pair of source and drain layer prongs. The channel layer portions are arranged in spaces between the gate prongs. There is also provided a method for forming a FET device.

公开(公告)号：US20220271755A1

公开(公告)日：2022-08-25

申请号：US17740759

申请日：2022-05-10

Applicant: IMEC VZW

Inventor： Francky CATTHOOR ,  Edouard GIACOMIN ,  Juergen BOEMMELS ,  Julien RYCKAERT

IPC: H03K19/17736 ,  H01L27/06

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell.

公开(公告)号：US20220109447A1

公开(公告)日：2022-04-07

申请号：US17063003

申请日：2020-10-05

Applicant: IMEC VZW

Inventor： Francky CATTHOOR ,  Edouard GIACOMIN ,  Juergen BOEMMELS ,  Julien RYCKAERT

IPC: H03K19/17736 ,  H01L27/06

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell.