公开(公告)号：US20220199809A1

公开(公告)日：2022-06-23

申请号：US17550383

申请日：2021-12-14

Applicant: IMEC VZW

Inventor： Julien RYCKAERT ,  Naoto HORIGUCHI ,  Boon Teik CHAN

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8234

Abstract: According to an aspect there is provided a FET device. The FET device comprises a common source body portion and a set of source layer prongs protruding therefrom in a first lateral direction. First dielectric layer portions are arranged in spaces between the source layer prongs. The device further comprises a common drain body portion and a set of drain layer prongs protruding in the first lateral direction. Second dielectric layer portions are arranged in spaces between the drain layer prongs. The device further comprises a gate body comprising a common gate body portion and a set of gate prongs protruding therefrom in a second lateral direction opposite the first lateral direction. Each gate prong is formed intermediate a respective pair of first and second dielectric layer portions. The device further comprises a channel region comprising a set of channel layer portions. Each channel layer portion extends between a respective pair of source and drain layer prongs. The channel layer portions are arranged in spaces between the gate prongs. There is also provided a method for forming a FET device.

公开(公告)号：US20220093734A1

公开(公告)日：2022-03-24

申请号：US17476747

申请日：2021-09-16

Applicant: IMEC VZW

Inventor： Boon Teik CHAN ,  Hans MERTENS ,  Eugenio DENTONI LITTA

IPC: H01L29/06 ,  H01L29/786

Abstract: A method for forming a semiconductor device is provided. The method comprises forming a device layer stack comprising an alternating sequence of lower sacrificial layers and channel layers, and a top sacrificial layer over the topmost channel layer, wherein the top sacrificial layer is thicker than each lower sacrificial layer; etching the top sacrificial layer to form a top sacrificial layer portion underneath the sacrificial gate structure; forming a first spacer on end surfaces of the top sacrificial layer portion; etching the channel and lower sacrificial layers while using the first spacer as an etch mask to form channel layer portions and lower sacrificial layer portions; etching the lower sacrificial layer portions to form recesses in the device layer stack, while the first spacer masks the end surfaces of the top sacrificial layer portion; and forming a second spacer in the recesses.

公开(公告)号：US20250133815A1

公开(公告)日：2025-04-24

申请号：US18923487

申请日：2024-10-22

Applicant: IMEC VZW

Inventor： Antony Premkumar PETER ,  Alfonso SEPULVEDA MARQUEZ ,  Boon Teik CHAN ,  Steven DEMUYNCK ,  Lucas PETERSEN BARBOSA LIMA ,  Victor Hugo VEGA GONZALEZ

IPC: H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: The disclosure relates to a method for processing a complementary field effect transistor, CFET, device. The method comprises the steps of forming at least one fin structure on a substrate, wherein the at least one fin structure comprises a horizontal top surface and two vertically oriented side surfaces between the top surface and the substrate, and wherein the at least one fin structure comprises a first layer stack and a second layer stack above the first layer stack, and forming a gate dielectric layer with a non-uniform layer thickness around the at least one fin structure, wherein the layer thickness of the gate dielectric layer which is arranged on the top surface of the at least one fin structure is larger than the layer thickness of the gate dielectric layer which is arranged on the side surfaces of the at least one fin structure.

公开(公告)号：US20220122895A1

公开(公告)日：2022-04-21

申请号：US17504842

申请日：2021-10-19

Applicant: IMEC VZW

Inventor： Boon Teik CHAN ,  Hans MERTENS

IPC: H01L21/8238 ,  H01L27/092

Abstract: According to an aspect of the present inventive concept there is provided a method for forming source/drain contacts, the method comprising: depositing a material layer over a first and second layer stack formed in a first and second device region of a substrate, respectively, each layer stack comprising a number of semiconductor channel layers and the layer stacks being separated by a trench filled with insulating material to form an insulating wall between the layer stacks and between the device regions; forming a contact partition trench in the material layer at a position above the insulating wall, and filling the contact partition trench with an insulating material to form a contact partition wall on top of the insulating wall; forming a first and a second source/drain contact trench on mutually opposite sides of the contact partition wall, the first source/drain contact trench being formed above a source/drain region in the first device region, and the second source/drain contact trench being formed above a source/drain region in the second device region, and the source/drain regions in the first and the second device region being separated by the insulating wall; and forming a first contact in the first source/drain contact trench and a second contact in the second source/drain contact trench, wherein the first and second contacts are separated by the contact partition wall.