公开(公告)号：US20220076383A1

公开(公告)日：2022-03-10

申请号：US17366350

申请日：2021-07-02

Applicant: IMEC VZW

Inventor： Bappaditya Dey ,  Sandip Halder ,  Gouri Sankar Kar ,  Victor M. Blanco ,  Senthil Srinivasan Shanmugam Vadakupudhu Palayam

IPC: G06T5/00

Abstract: The disclosure relates generally to image processing. For example, the invention relates to a method and a device for de-noising an electron microscope (EM) image. The method includes the act of selecting a patch of the EM image, wherein the patch comprises a plurality of pixels, wherein the following acts are performed on the patch: i) replacing the value of one pixel, for example of a center pixel, of the patch with the value of a different, for example randomly selected, pixel from the same EM image; ii) determining a de-noised value for the one pixel based on the values of the other pixels in the patch; and iii) replacing the value of the one pixel with the determined de-noised value.

公开(公告)号：US20210335611A1

公开(公告)日：2021-10-28

申请号：US17238111

申请日：2021-04-22

Applicant: IMEC VZW

Inventor： Frederic Lazzarino ,  Victor M. Blanco

IPC: H01L21/033 ,  H01L21/768

Abstract: A method that provides patterning of an underlying layer to form a first set of trenches and a second set of trenches in the underlying layer is based on a combination of two litho-etch (LE) patterning processes supplemented with a spacer-assisted (SA) technique. The method uses a layer stack comprising three memorization layers: an upper memorization layer allowing first memorizing upper trenches, and then one or more upper blocks; an intermediate memorization layer allowing first memorizing intermediate trenches and one or more first intermediate blocks, and then second intermediate blocks and intermediate lines; and a lower memorization layer allowing first memorizing first lower trenches and one or more first lower blocks, and then second lower trenches and one or more second lower blocks.

公开(公告)号：US11476155B2

公开(公告)日：2022-10-18

申请号：US17237699

申请日：2021-04-22

Applicant: IMEC VZW

Inventor： Victor M. Blanco ,  Frederic Lazzarino

IPC: H01L21/768 ,  H01L21/033

Abstract: A method that provides patterning of an underlying layer to form a first set of trenches and a second set of trenches in the underlying layer is based on a combination of two litho-etch (LE) patterning processes supplemented with a spacer-assisted (SA) technique. The method uses one or more first upper blocks formed by a tone-inversion approach, an upper memorization layer allowing first memorizing upper trenches, and then second upper blocks, and a lower memorization layer allowing first memorizing first lower trenches and one or more first lower blocks, and then second lower trenches and one or more second lower blocks.

公开(公告)号：US20210335664A1

公开(公告)日：2021-10-28

申请号：US17237699

申请日：2021-04-22

Applicant: IMEC VZW

Inventor： Victor M. Blanco ,  Frederic Lazzarino

IPC: H01L21/768 ,  H01L21/48 ,  H01L21/033

Abstract: A method that provides patterning of an underlying layer to form a first set of trenches and a second set of trenches in the underlying layer is based on a combination of two litho-etch (LE) patterning processes supplemented with a spacer-assisted (SA) technique. The method uses one or more first upper blocks formed by a tone-inversion approach, an upper memorization layer allowing first memorizing upper trenches, and then second upper blocks, and a lower memorization layer allowing first memorizing first lower trenches and one or more first lower blocks, and then second lower trenches and one or more second lower blocks.

公开(公告)号：US12243193B2

公开(公告)日：2025-03-04

申请号：US17366350

申请日：2021-07-02

Applicant: IMEC VZW

Inventor： Bappaditya Dey ,  Sandip Halder ,  Gouri Sankar Kar ,  Victor M. Blanco ,  Senthil Srinivasan Shanmugam Vadakupudhu Palayam

IPC: G06T5/70 ,  G06T5/50

Abstract: The disclosure relates generally to image processing. For example, the invention relates to a method and a device for de-noising an electron microscope (EM) image. The method includes the act of selecting a patch of the EM image, wherein the patch comprises a plurality of pixels, wherein the following acts are performed on the patch: i) replacing the value of one pixel, for example of a center pixel, of the patch with the value of a different, for example randomly selected, pixel from the same EM image; ii) determining a de-noised value for the one pixel based on the values of the other pixels in the patch; and iii) replacing the value of the one pixel with the determined de-noised value.

公开(公告)号：US20200075335A1

公开(公告)日：2020-03-05

申请号：US16556124

申请日：2019-08-29

Applicant: IMEC VZW

Inventor： Frederic Lazzarino ,  Victor M. Blanco

IPC: H01L21/033 ,  H01L21/311

Abstract: An example embodiment includes a patterning method comprising: forming a layer stack comprising a target layer, a lower memorization layer and an upper memorization layer, forming above the upper memorization layer a first mask layer, patterning a set of upper trenches in the upper memorization layer, forming a first block pattern, the first block pattern comprising a set of first blocks, patterning a first set of lower trenches in the lower memorization layer, patterning the patterned upper memorization layer to form a second block pattern comprising a set of second blocks, forming above the patterned lower memorization layer and the second block pattern a second mask layer, patterning a second set of lower trenches in the patterned lower memorization layer, the patterning comprising using the second mask layer, the spacer layer and the second block pattern as an etch mask.

公开(公告)号：US12261045B2

公开(公告)日：2025-03-25

申请号：US17567361

申请日：2022-01-03

Applicant: IMEC VZW

Inventor： Victor M. Blanco ,  Frederic Lazzarino

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3213

Abstract: According to an aspect there is provided a patterning method comprising: over a lower pattern memorization layer, forming a pattern of first upper blocks, then an upper pattern memorization layer and then a pattern of second upper blocks; thereafter patterning upper trenches in the upper pattern memorization layer using lithography and etching, and forming spacer lines along sidewalls of the upper trenches to define spacer-provided upper trenches, at least a subset being interrupted by a respective first upper block; patterning first lower trenches in the lower pattern memorization layer by etching the spacer-provided upper trenches into the lower pattern memorization layer, at least a subset of the first lower trenches being interrupted by a lower pattern memorization layer portion preserved at a location defined by a respective one of the first upper blocks; thereafter, forming an auxiliary trench mask stack and patterning auxiliary trenches therein using lithography and etching; and thereafter, patterning the second lower trenches in the lower pattern memorization layer, the patterning comprising using the patterned auxiliary trench mask stack, the spacer lines and the second upper blocks as etch masks, at least a subset of the second lower trenches being interrupted by a lower pattern memorization layer portion preserved at a position defined by a respective one of the second upper blocks.

公开(公告)号：US11710637B2

公开(公告)日：2023-07-25

申请号：US17238111

申请日：2021-04-22

Applicant: IMEC VZW

Inventor： Frederic Lazzarino ,  Victor M. Blanco

IPC: H01L21/033 ,  H01L21/768

CPC classification number: H01L21/0338 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/76816 ,  H01L21/76877

Abstract: A method that provides patterning of an underlying layer to form a first set of trenches and a second set of trenches in the underlying layer is based on a combination of two litho-etch (LE) patterning processes supplemented with a spacer-assisted (SA) technique. The method uses a layer stack comprising three memorization layers: an upper memorization layer allowing first memorizing upper trenches, and then one or more upper blocks; an intermediate memorization layer allowing first memorizing intermediate trenches and one or more first intermediate blocks, and then second intermediate blocks and intermediate lines; and a lower memorization layer allowing first memorizing first lower trenches and one or more first lower blocks, and then second lower trenches and one or more second lower blocks.

公开(公告)号：US10770295B2

公开(公告)日：2020-09-08

申请号：US16556124

申请日：2019-08-29

Applicant: IMEC VZW

Inventor： Frederic Lazzarino ,  Victor M. Blanco

IPC: H01L21/033 ,  H01L21/311

Abstract: An example embodiment includes a patterning method comprising: forming a layer stack comprising a target layer, a lower memorization layer and an upper memorization layer, forming above the upper memorization layer a first mask layer, patterning a set of upper trenches in the upper memorization layer, forming a first block pattern, the first block pattern comprising a set of first blocks, patterning a first set of lower trenches in the lower memorization layer, patterning the patterned upper memorization layer to form a second block pattern comprising a set of second blocks, forming above the patterned lower memorization layer and the second block pattern a second mask layer, patterning a second set of lower trenches in the patterned lower memorization layer, the patterning comprising using the second mask layer, the spacer layer and the second block pattern as an etch mask.