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公开(公告)号:US20200075335A1
公开(公告)日:2020-03-05
申请号:US16556124
申请日:2019-08-29
Applicant: IMEC VZW
Inventor: Frederic Lazzarino , Victor M. Blanco
IPC: H01L21/033 , H01L21/311
Abstract: An example embodiment includes a patterning method comprising: forming a layer stack comprising a target layer, a lower memorization layer and an upper memorization layer, forming above the upper memorization layer a first mask layer, patterning a set of upper trenches in the upper memorization layer, forming a first block pattern, the first block pattern comprising a set of first blocks, patterning a first set of lower trenches in the lower memorization layer, patterning the patterned upper memorization layer to form a second block pattern comprising a set of second blocks, forming above the patterned lower memorization layer and the second block pattern a second mask layer, patterning a second set of lower trenches in the patterned lower memorization layer, the patterning comprising using the second mask layer, the spacer layer and the second block pattern as an etch mask.
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公开(公告)号:US09437488B2
公开(公告)日:2016-09-06
申请号:US14939286
申请日:2015-11-12
Applicant: IMEC VZW
Inventor: Boon Teik Chan , Silvia Armini , Frederic Lazzarino
IPC: H01L21/4763 , H01L21/768 , H01L21/311 , H01L21/321 , H01L21/3105 , H01L23/532
CPC classification number: H01L21/76877 , H01L21/31053 , H01L21/31144 , H01L21/3212 , H01L21/76808 , H01L21/76814 , H01L21/76816 , H01L21/7682 , H01L21/76831 , H01L21/76832 , H01L21/7684 , H01L21/76843 , H01L21/76852 , H01L21/76871 , H01L21/76885 , H01L23/53238 , H01L2221/1026 , H01L2221/1063 , H01L2924/0002 , H01L2924/00
Abstract: A method is provided for fabricating a semiconductor device that includes providing a structure with a sacrificial layer having at least one through-hole exposing a metal surface and, optionally, an oxide surface. In one example, the method may include applying a self-assembled monolayer selectively on the exposed metal surface and/or on the oxide surface. The method may also include growing a metal on the self-assembled monolayer and on the exposed metal surface if no self-assembled monolayer is present thereon, so as to fill the at least one through-hole, thereby forming at least one metal structure. The method may further include replacing the first sacrificial layer by a replacement dielectric layer having a dielectric constant of at most 3.9.
Abstract translation: 提供了一种用于制造半导体器件的方法,该半导体器件包括提供具有牺牲层的结构,所述牺牲层具有暴露金属表面和任选地氧化物表面的至少一个通孔。 在一个实例中,该方法可以包括在暴露的金属表面和/或氧化物表面上选择性地应用自组装单层。 该方法还可以包括在自组装单层上和暴露的金属表面上生长金属,如果不存在自组装单层,以便填充至少一个通孔,从而形成至少一个金属结构。 该方法还可以包括通过介电常数至多为3.9的置换介电层代替第一牺牲层。
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公开(公告)号:US20160155664A1
公开(公告)日:2016-06-02
申请号:US14939286
申请日:2015-11-12
Applicant: IMEC VZW
Inventor: Boon Teik Chan , Silvia Armini , Frederic Lazzarino
IPC: H01L21/768 , H01L23/532 , H01L21/3105 , H01L21/311 , H01L21/321
CPC classification number: H01L21/76877 , H01L21/31053 , H01L21/31144 , H01L21/3212 , H01L21/76808 , H01L21/76814 , H01L21/76816 , H01L21/7682 , H01L21/76831 , H01L21/76832 , H01L21/7684 , H01L21/76843 , H01L21/76852 , H01L21/76871 , H01L21/76885 , H01L23/53238 , H01L2221/1026 , H01L2221/1063 , H01L2924/0002 , H01L2924/00
Abstract: A method is provided for fabricating a semiconductor device that includes providing a structure with a sacrificial layer having at least one through-hole exposing a metal surface and, optionally, an oxide surface. In one example, the method may include applying a self-assembled monolayer selectively on the exposed metal surface and/or on the oxide surface. The method may also include growing a metal on the self-assembled monolayer and on the exposed metal surface if no self-assembled monolayer is present thereon, so as to fill the at least one through-hole, thereby forming at least one metal structure. The method may further include replacing the first sacrificial layer by a replacement dielectric layer having a dielectric constant of at most 3.9.
Abstract translation: 提供了一种用于制造半导体器件的方法,该半导体器件包括提供具有牺牲层的结构,所述牺牲层具有暴露金属表面和任选地氧化物表面的至少一个通孔。 在一个实例中,该方法可以包括在暴露的金属表面和/或氧化物表面上选择性地应用自组装单层。 该方法还可以包括在自组装单层上和暴露的金属表面上生长金属,如果不存在自组装单层,以便填充至少一个通孔,从而形成至少一个金属结构。 该方法还可以包括通过介电常数至多为3.9的置换介电层代替第一牺牲层。
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公开(公告)号:US20210335611A1
公开(公告)日:2021-10-28
申请号:US17238111
申请日:2021-04-22
Applicant: IMEC VZW
Inventor: Frederic Lazzarino , Victor M. Blanco
IPC: H01L21/033 , H01L21/768
Abstract: A method that provides patterning of an underlying layer to form a first set of trenches and a second set of trenches in the underlying layer is based on a combination of two litho-etch (LE) patterning processes supplemented with a spacer-assisted (SA) technique. The method uses a layer stack comprising three memorization layers: an upper memorization layer allowing first memorizing upper trenches, and then one or more upper blocks; an intermediate memorization layer allowing first memorizing intermediate trenches and one or more first intermediate blocks, and then second intermediate blocks and intermediate lines; and a lower memorization layer allowing first memorizing first lower trenches and one or more first lower blocks, and then second lower trenches and one or more second lower blocks.
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公开(公告)号:US10818504B2
公开(公告)日:2020-10-27
申请号:US16218749
申请日:2018-12-13
Applicant: IMEC VZW
Inventor: Waikin Li , Danilo De Simone , Sandip Halder , Frederic Lazzarino
IPC: H01L21/308 , G03F7/20 , G03F1/70
Abstract: A method for producing a pattern of features on a substrate may involve performing two exposure steps on a resist layer applied to the substrate, followed by a single etching step. In the two exposures, the same pattern of mask features is used, but with possibly differing dimensions and with the pattern applied in the second exposure being shifted in position relative to the pattern in the first exposure. The shift, lithographic parameters, and/or possibly differing dimensions are configured such that a number of resist areas exposed in the second exposure overlap one or more resist areas exposed in the first exposure. When the pattern of mask features is a regular 2-dimensional array, the method produces of an array of holes or pillars that is denser than the original array. Varying the mask patterns can produce different etched structure shapes, such as a zig-zag pattern.
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公开(公告)号:US20180247814A1
公开(公告)日:2018-08-30
申请号:US15906149
申请日:2018-02-27
Applicant: IMEC VZW
Inventor: Frederic Lazzarino
IPC: H01L21/033 , H01L21/768 , H01L21/311 , H01L21/027
CPC classification number: H01L21/0337 , H01L21/0273 , H01L21/0332 , H01L21/31116 , H01L21/31127 , H01L21/31144 , H01L21/76802 , H01L21/76816 , H01L21/76877
Abstract: An example embodiment may include a method for defining patterns for conductive paths in a dielectric layer. The method may include (a) forming a mask layer on the dielectric layer, (b) forming on the mask layer a set of longitudinally and parallel extending mask features, each mask feature including a mandrel having a pair of side wall spacers, the mask features being spaced apart such that gaps are formed between the mask features, (c) depositing an organic spin-on layer covering the set of mask features and filling the gaps, (d) etching a first trench in the organic spin-on layer, the first trench extending across at least a subset of the gaps and exposing the mask layer, and (e) depositing in a spin-on process a planarization layer covering the organic spin-on layer and filling the first trench.
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公开(公告)号:US11476155B2
公开(公告)日:2022-10-18
申请号:US17237699
申请日:2021-04-22
Applicant: IMEC VZW
Inventor: Victor M. Blanco , Frederic Lazzarino
IPC: H01L21/768 , H01L21/033
Abstract: A method that provides patterning of an underlying layer to form a first set of trenches and a second set of trenches in the underlying layer is based on a combination of two litho-etch (LE) patterning processes supplemented with a spacer-assisted (SA) technique. The method uses one or more first upper blocks formed by a tone-inversion approach, an upper memorization layer allowing first memorizing upper trenches, and then second upper blocks, and a lower memorization layer allowing first memorizing first lower trenches and one or more first lower blocks, and then second lower trenches and one or more second lower blocks.
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公开(公告)号:US20210335664A1
公开(公告)日:2021-10-28
申请号:US17237699
申请日:2021-04-22
Applicant: IMEC VZW
Inventor: Victor M. Blanco , Frederic Lazzarino
IPC: H01L21/768 , H01L21/48 , H01L21/033
Abstract: A method that provides patterning of an underlying layer to form a first set of trenches and a second set of trenches in the underlying layer is based on a combination of two litho-etch (LE) patterning processes supplemented with a spacer-assisted (SA) technique. The method uses one or more first upper blocks formed by a tone-inversion approach, an upper memorization layer allowing first memorizing upper trenches, and then second upper blocks, and a lower memorization layer allowing first memorizing first lower trenches and one or more first lower blocks, and then second lower trenches and one or more second lower blocks.
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公开(公告)号:US10707198B2
公开(公告)日:2020-07-07
申请号:US16014888
申请日:2018-06-21
Applicant: IMEC VZW
Inventor: Frederic Lazzarino
IPC: H01L23/528 , H01L27/02 , H01L21/033 , H01L21/02 , H01L21/768
Abstract: A method is provided for patterning a target layer, the method comprising: (i) forming above the target layer a line mask and a mandrel mask, wherein forming the line mask comprises forming parallel material lines extending in a longitudinal direction, wherein forming the mandrel mask comprises forming a mandrel mask having sidewalls including at least a first sidewall extending transverse to a plurality of the material lines; (ii) forming on the sidewalls of the mandrel mask a sidewall spacer including a first sidewall spacer portion extending along the first sidewall; (iii) partially removing the sidewall spacer such that a remainder of the sidewall spacer comprises at least a part of the first sidewall spacer portion; and (iv) subsequent to removing the mandrel mask, transferring into the target layer a pattern defined by the line mask and the remainder of the sidewall spacer.
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公开(公告)号:US10593549B2
公开(公告)日:2020-03-17
申请号:US15906149
申请日:2018-02-27
Applicant: IMEC VZW
Inventor: Frederic Lazzarino
IPC: H01L21/311 , H01L21/027 , H01L21/033 , H01L21/3213 , H01L21/768
Abstract: An example embodiment may include a method for defining patterns for conductive paths in a dielectric layer. The method may include (a) forming a mask layer on the dielectric layer, (b) forming on the mask layer a set of longitudinally and parallel extending mask features, each mask feature including a mandrel having a pair of side wall spacers, the mask features being spaced apart such that gaps are formed between the mask features, (c) depositing an organic spin-on layer covering the set of mask features and filling the gaps, (d) etching a first trench in the organic spin-on layer, the first trench extending across at least a subset of the gaps and exposing the mask layer, and (e) depositing in a spin-on process a planarization layer covering the organic spin-on layer and filling the first trench.
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