公开(公告)号：US20220157704A1

公开(公告)日：2022-05-19

申请号：US17524121

申请日：2021-11-11

Applicant: IMEC VZW

Inventor： Gaspard HIBLOT ,  Geert VAN DER PLAS

IPC: H01L23/498 ,  A61B5/279 ,  A61B5/263 ,  H01L23/48

Abstract: An electrode arrangement comprises: a semiconductor carrier substrate having a first and a second side surface; a first array of electrodes arranged above the first side surface; a second array of electrodes arranged below the second side surface; an electronic circuitry for processing electrical signals recorded by the electrodes; a connecting layer arranged above the electronic circuitry and providing a first connection between a first point and a second point; a first interconnect for electrically connecting the first point to the electronic circuitry; a second interconnect and a first through-substrate via which electrically connect the second point to the electrode in the second array.

公开(公告)号：US20230178478A1

公开(公告)日：2023-06-08

申请号：US17991351

申请日：2022-11-21

Applicant: IMEC VZW

Inventor： Gaspard HIBLOT ,  Douglas Charles LA TULIPE ,  Anne JOURDAIN

IPC: H01L23/522 ,  H01L23/48 ,  H01L21/02 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L23/5226 ,  H01L21/02019 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827

Abstract: A method producing a nano-sized interconnect structure that electrically connects the front side of a semiconductor substrate to the back side of the substrate is provided. In one aspect, the method produces a semiconductor component such as an integrated circuit chip that includes active devices formed on the front side of the substrate, and an interconnect network such as a power delivery network on the back side of the substrate. The substrate includes a lower semiconductor layer, an intermediate layer, and an upper layer. A trench is formed through the upper layer, the material of the intermediate layer is etched from inside the trench to form a cavity at the foot of the trench, and the trench and the cavity are filled with an electrically conductive material to form a buried rail with a wide contact pad at the foot of the rail, that is, wider than the width of the rail and extending between the front and back surfaces of the intermediate layer. A nanoTSV connection is processed from the back of the substrate, the nanoTSV contacting the contact pad, to thereby form the interconnect structure.

公开(公告)号：US20220238388A1

公开(公告)日：2022-07-28

申请号：US17580020

申请日：2022-01-20

Applicant: IMEC vzw

Inventor： Gaspard HIBLOT ,  Anshul GUPTA ,  Geert VAN DER PLAS

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method of producing a gate cut in a semiconductor component is provided. In one aspect, an array of nano-sized semiconductor fins is processed on a semiconductor substrate. Rails may be buried in the substrate and in a layer of dielectric material that isolates neighboring fins from each other. The rails may extend in the direction of the fins and each rail may be situated between two adjacent fins. The rails may be buried power rails for enabling the formation of a power delivery network at the back of an integrated circuit chip. At the front side of the substrate, one or more gate structures are produced. The gate structures extend transversally, or perpendicularly, with respect to the fins and the rails. A gate cut is produced by forming an opening from the back side of the substrate, and removing a portion of the gate structure at the bottom of the opening, thereby creating a gate cut that is aligned to the sidewalls of the rail. In another aspect, a semiconductor component, such as an integrated circuit, includes a gate cut that is aligned to the sidewalls of a buried contact rail.