公开(公告)号：US20220238388A1

公开(公告)日：2022-07-28

申请号：US17580020

申请日：2022-01-20

Applicant: IMEC vzw

Inventor： Gaspard HIBLOT ,  Anshul GUPTA ,  Geert VAN DER PLAS

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method of producing a gate cut in a semiconductor component is provided. In one aspect, an array of nano-sized semiconductor fins is processed on a semiconductor substrate. Rails may be buried in the substrate and in a layer of dielectric material that isolates neighboring fins from each other. The rails may extend in the direction of the fins and each rail may be situated between two adjacent fins. The rails may be buried power rails for enabling the formation of a power delivery network at the back of an integrated circuit chip. At the front side of the substrate, one or more gate structures are produced. The gate structures extend transversally, or perpendicularly, with respect to the fins and the rails. A gate cut is produced by forming an opening from the back side of the substrate, and removing a portion of the gate structure at the bottom of the opening, thereby creating a gate cut that is aligned to the sidewalls of the rail. In another aspect, a semiconductor component, such as an integrated circuit, includes a gate cut that is aligned to the sidewalls of a buried contact rail.

公开(公告)号：US20230170297A1

公开(公告)日：2023-06-01

申请号：US17991255

申请日：2022-11-21

Applicant: IMEC VZW

Inventor： Shih-Hung CHEN ,  Eric BEYNE ,  Geert VAN DER PLAS

IPC: H01L23/522 ,  H01L27/02 ,  H01L27/105 ,  H01L23/492 ,  H01L23/60 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L23/60 ,  H01L23/4926 ,  H01L24/02 ,  H01L27/105 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0292 ,  H01L2224/02373

Abstract: A semiconductor component, for example an integrated circuit chip, including a semiconductor substrate having active devices at the front side thereof and I/O terminals at the back side of the component, is provided. In one aspect, the terminals are connected to the active devices through TSV connections and buried rails in an area of the substrate that is separate from the area in which the active devices are located. The I/O TSV connections are located in a floating well of the substrate that is separated from the rest of the substrate by a second well formed of material of the opposite conductivity type compared to the material of the floating well. The second well includes at least one contact configured to be coupled to a voltage that is suitable for reverse-biasing the junction between the floating well and the second well. A small capacitance is placed in series with the large parasitic capacitance generated by a thin dielectric liner that isolates the I/O TSVs and I/O rails from the substrate, thereby mitigating the negative effect of the large parasitic capacitance. Additional contacts and conductors can be provided which are configured to create an ESD protection circuit for protecting the I/O TSVs and the I/O rails from electrostatic discharges.

公开(公告)号：US20220157704A1

公开(公告)日：2022-05-19

申请号：US17524121

申请日：2021-11-11

Applicant: IMEC VZW

Inventor： Gaspard HIBLOT ,  Geert VAN DER PLAS

IPC: H01L23/498 ,  A61B5/279 ,  A61B5/263 ,  H01L23/48

Abstract: An electrode arrangement comprises: a semiconductor carrier substrate having a first and a second side surface; a first array of electrodes arranged above the first side surface; a second array of electrodes arranged below the second side surface; an electronic circuitry for processing electrical signals recorded by the electrodes; a connecting layer arranged above the electronic circuitry and providing a first connection between a first point and a second point; a first interconnect for electrically connecting the first point to the electronic circuitry; a second interconnect and a first through-substrate via which electrically connect the second point to the electrode in the second array.