公开(公告)号：US10756035B2

公开(公告)日：2020-08-25

申请号：US15285250

申请日：2016-10-04

Applicant: Infineon Technologies AG

Inventor： Roman Roth ,  Wolfgang Wagner

IPC: H01L23/00

Abstract: A semiconductor device is presented. The semiconductor device comprises a semiconductor body coupled to a first load terminal and to a second load terminal and configured to carry a load current between the first load terminal and the second load terminal. The first load terminal comprises a contiguous metal layer coupled to the semiconductor body; and at least one metal island arranged on top of and in contact with the contiguous metal layer and configured to be contacted by an end of a bond wire and to receive at least a part of the load current by means of the bond wire, wherein the contiguous metal layer and the metal island are composed of the same metal.

公开(公告)号：US20200013722A1

公开(公告)日：2020-01-09

申请号：US16577316

申请日：2019-09-20

Applicant: Infineon Technologies AG

Inventor： Frank Hille ,  Ravi Keshav Joshi ,  Michael Fugger ,  Oliver Humbel ,  Thomas Laska ,  Matthias Müller ,  Roman Roth ,  Carsten Schaeffer ,  Hans-Joachim Schulze ,  Holger Schulze ,  Juergen Steinbrenner ,  Frank Umbach

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.

公开(公告)号：US09859272B2

公开(公告)日：2018-01-02

申请号：US15210449

申请日：2016-07-14

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Holger Huesken ,  Franz-Josef Niedernostheide ,  Frank Dieter Pfirsch ,  Roman Roth ,  Christian Philipp Sandow ,  Carsten Schaeffer ,  Stephan Voss

IPC: H01L29/66 ,  H01L27/06 ,  H01L29/739 ,  H01L29/10 ,  H01L29/45 ,  H01L29/47 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L27/0664 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/205 ,  H01L29/45 ,  H01L29/47 ,  H01L29/7397 ,  H01L29/8611 ,  H01L29/8613 ,  H01L29/868 ,  H01L29/872

Abstract: A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C). The semiconductor body region isolates the source region from the drift region and includes a reduced band gap zone comprising a second semiconductor material (M2) having a second band gap that is smaller than the first band gap, wherein the reduced band gap zone is arranged in the semiconductor body region such that the reduced band gap zone and the source region exhibit, in a cross-section along a vertical direction (Z), at least one of a common lateral extension range (LR) along a first lateral direction (X) and a common vertical extension range (VR) along the vertical direction (Z).

公开(公告)号：US20170271268A1

公开(公告)日：2017-09-21

申请号：US15458366

申请日：2017-03-14

Applicant: Infineon Technologies AG

Inventor： Frank Hille ,  Ravi Keshav Joshi ,  Michael Fugger ,  Oliver Humbel ,  Thomas Laska ,  Matthias Mueller ,  Roman Roth ,  Carsten Schaeffer ,  Hans-Joachim Schulze ,  Holger Schulze ,  Juergen Steinbrenner ,  Frank Umbach

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53209 ,  H01L21/76846 ,  H01L21/76861 ,  H01L21/76898 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238

Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.

公开(公告)号：US10079217B2

公开(公告)日：2018-09-18

申请号：US15420815

申请日：2017-01-31

Applicant: Infineon Technologies AG

Inventor： Roman Roth ,  Frank Hille ,  Hans-Joachim Schulze

IPC: H01L23/00

Abstract: A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.

公开(公告)号：US10777506B2

公开(公告)日：2020-09-15

申请号：US16577316

申请日：2019-09-20

Applicant: Infineon Technologies AG

Inventor： Frank Hille ,  Ravi Keshav Joshi ,  Michael Fugger ,  Oliver Humbel ,  Thomas Laska ,  Matthias Müller ,  Roman Roth ,  Carsten Schaeffer ,  Hans-Joachim Schulze ,  Holger Schulze ,  Juergen Steinbrenner ,  Frank Umbach

IPC: H01L23/532 ,  H01L23/485 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.

公开(公告)号：US10224237B2

公开(公告)日：2019-03-05

申请号：US15602451

申请日：2017-05-23

Applicant: Infineon Technologies AG

Inventor： Roman Roth ,  Frank Umbach

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: A method for forming a semiconductor device includes forming an insulating material layer above a semiconductor substrate and modifying at least a portion of a surface of the insulating material layer after forming the insulating material layer. Further, the method includes forming an electrical conductive structure on at least the portion of the surface of the insulating material layer after modifying at least the portion of the surface of the insulating material layer.

公开(公告)号：US09773736B2

公开(公告)日：2017-09-26

申请号：US14607708

申请日：2015-01-28

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Juergen Steinbrenner ,  Christian Fachmann ,  Petra Fischer ,  Roman Roth

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L21/3213

CPC classification number: H01L23/53238 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/76885 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.

公开(公告)号：US20170025408A1

公开(公告)日：2017-01-26

申请号：US15210449

申请日：2016-07-14

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Holger Huesken ,  Franz-Josef Niedernostheide ,  Frank Dieter Pfirsch ,  Roman Roth ,  Christian Philipp Sandow ,  Carsten Schaeffer ,  Stephan Voss

IPC: H01L27/06 ,  H01L29/10 ,  H01L29/739

CPC classification number: H01L27/0664 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/205 ,  H01L29/45 ,  H01L29/47 ,  H01L29/7397 ,  H01L29/8611 ,  H01L29/8613 ,  H01L29/868 ,  H01L29/872

Abstract: A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C).The semiconductor body region isolates the source region from the drift region and includes a reduced band gap zone comprising a second semiconductor material (M2) having a second band gap that is smaller than the first band gap, wherein the reduced band gap zone is arranged in the semiconductor body region such that the reduced band gap zone and the source region exhibit, in a cross-section along a vertical direction (Z), at least one of a common lateral extension range (LR) along a first lateral direction (X) and a common vertical extension range (VR) along the vertical direction (Z).

Abstract translation: 一种半导体器件，包括电连接到半导体器件的第一负载端子（E）的源极区域和包括具有第一带隙的第一半导体材料（M1）的漂移区域，所述漂移区域具有第一导电类型的掺杂剂 并且被配置为在半导体器件的第一负载端子（E）和第二负载端子（C）之间承载至少一部分负载电流。 半导体器件还包括具有与第一导电类型互补的第二导电类型的掺杂剂并且与第一负载端子（E）电连接的半导体本体区域，在半导体主体区域和漂移区域之间形成pn- 其中所述pn结被配置为阻挡施加在所述第一负载端子（E）和所述第二负载端子（C）之间的电压。所述半导体体区域将所述源极区域与所述漂移区域隔离，并且包括减小的带隙区域 包括具有小于所述第一带隙的第二带隙的第二半导体材料（M2），其中所述还原带隙区域布置在所述半导体主体区域中，使得所述还原带隙区域和所述源极区域在 沿着垂直方向（Z）的横截面，沿着第一横向方向（X）的公共横向延伸范围（LR）和公共垂直伸展中的至少一个 离子范围（VR）沿垂直方向（Z）。

公开(公告)号：US11315892B2

公开(公告)日：2022-04-26

申请号：US16059468

申请日：2018-08-09

Applicant: Infineon Technologies AG

Inventor： Roman Roth ,  Frank Hille ,  Hans-Joachim Schulze

IPC: H01L23/00 ,  H01L23/532 ,  H01L21/768

Abstract: A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.