公开(公告)号：US09349794B2

公开(公告)日：2016-05-24

申请号：US14287222

申请日：2014-05-27

Applicant: Infineon Technologies AG

Inventor： Gopalakrishnan Trichy Rengarajan ,  Christian Fachmann

IPC: H01L29/06 ,  H01L21/285 ,  H01L21/74 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L29/0676 ,  H01L21/28506 ,  H01L21/3081 ,  H01L21/743 ,  H01L21/76882

Abstract: A layer arrangement in accordance with various embodiments may include: a first layer having a side; one or more nanoholes in the first layer that are open towards the side of the first layer; a second layer filling at least part of the nanoholes and covering at least part of the side of the first layer, the second layer including at least one of the following materials: a metal or metal alloy, a glass material, a polymer material, a ceramic material.

Abstract translation: 根据各种实施例的层布置可以包括：具有侧面的第一层; 第一层中朝向第一层侧面开口的一个或多个纳米孔; 填充所述纳米孔的至少一部分并覆盖所述第一层的至少一部分的第二层，所述第二层包括以下材料中的至少一种：金属或金属合金，玻璃材料，聚合物材料， 陶瓷材料。

公开(公告)号：US20160218033A1

公开(公告)日：2016-07-28

申请号：US14607708

申请日：2015-01-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ravi Keshav Joshi ,  Juergen Steinbrenner ,  Christian Fachmann ,  Petra Fischer ,  Roman Roth

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L23/53238 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/76885 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.

Abstract translation: 在半导体衬底上形成金属化层的方法包括在层间电介质层上沉积扩散阻挡衬垫的覆盖层，以及在扩散阻挡衬里上沉积中间层的覆盖层。 包含铜的功率金属层的覆盖层沉积在中间层上。 中间层包括多数元素和铜的固溶体。 中间层具有与功率金属层不同的蚀刻选择性。 在沉积功率金属层之后，构建功率金属层，中间层和扩散阻挡衬里。

公开(公告)号：US11527468B2

公开(公告)日：2022-12-13

申请号：US16568818

申请日：2019-09-12

Applicant: Infineon Technologies AG

Inventor： Andreas Riegler ,  Christian Fachmann ,  Matteo-Alessandro Kutschak ,  Carsten von Koblinski ,  Hans Weber

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/00 ,  H01L23/13 ,  H01L21/48

Abstract: A connection body which comprises a base structure at least predominantly made of a semiconductor oxide material or glass material, and an electrically conductive wiring structure on and/or in the base structure, wherein the electrically conductive wiring structure comprises at least one vertical wiring section with a first lateral dimension on and/or in the base structure and at least one lateral wiring section connected with the at least one vertical wiring section, wherein the at least one lateral wiring section has a second lateral dimension on and/or in the base structure, which is different to the first lateral dimension.

公开(公告)号：US09812373B2

公开(公告)日：2017-11-07

申请号：US14960804

申请日：2015-12-07

Applicant: Infineon Technologies AG

Inventor： Christian Fachmann ,  Ralf Otremba ,  Klaus Schiess ,  Franz Stueckler

IPC: H01L23/367 ,  H01L23/373 ,  F28F21/08 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/3672 ,  F28F21/081 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/3737 ,  H01L23/49551 ,  H01L24/00 ,  H01L2224/06181 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014

Abstract: An electronic module includes a semiconductor package including a semiconductor chip and an electrically insulating encapsulation body encapsulating the semiconductor chip, the encapsulation body completely covering a second main face and four side faces of the semiconductor chip, wherein a first main face of the semiconductor chip that is opposite the first main face is exposed from the encapsulation body, a heat spreader attached to the semiconductor package, the heat spreader completely covering the first main face of the semiconductor chip, and an electrically insulating layer disposed on the heat spreader remote from the semiconductor package. The electrically insulating layer is completely separated from the semiconductor chip.

公开(公告)号：US20200091058A1

公开(公告)日：2020-03-19

申请号：US16568818

申请日：2019-09-12

Applicant: Infineon Technologies AG

Inventor： Andreas Riegler ,  Christian Fachmann ,  Matteo-Alessandro Kutschak ,  Carsten von Koblinski ,  Hans Weber

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/00 ,  H01L23/13 ,  H01L21/48

Abstract: A connection body which comprises a base structure at least predominantly made of a semiconductor oxide material or glass material, and an electrically conductive wiring structure on and/or in the base structure, wherein the electrically conductive wiring structure comprises at least one vertical wiring section with a first lateral dimension on and/or in the base structure and at least one lateral wiring section connected with the at least one vertical wiring section, wherein the at least one lateral wiring section has a second lateral dimension on and/or in the base structure, which is different to the first lateral dimension.

公开(公告)号：US09773736B2

公开(公告)日：2017-09-26

申请号：US14607708

申请日：2015-01-28

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Juergen Steinbrenner ,  Christian Fachmann ,  Petra Fischer ,  Roman Roth

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L21/3213

CPC classification number: H01L23/53238 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/76885 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.

公开(公告)号：US20160163616A1

公开(公告)日：2016-06-09

申请号：US14960804

申请日：2015-12-07

Applicant: Infineon Technologies AG

Inventor： Christian Fachmann ,  Ralf Otremba ,  Klaus Schiess ,  Franz Stueckler

IPC: H01L23/367 ,  H01L23/373 ,  F28F21/08

CPC classification number: H01L23/3672 ,  F28F21/081 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/3737 ,  H01L23/49551 ,  H01L24/00 ,  H01L2224/06181 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014

Abstract: An electronic module includes a semiconductor package, a heat spreader attached to the semiconductor package and an electrically insulating layer disposed on the heat spreader remote from the semiconductor package.

Abstract translation: 电子模块包括半导体封装，附接到半导体封装的散热器和设置在远离半导体封装的散热器上的电绝缘层。