公开(公告)号：US09647825B2

公开(公告)日：2017-05-09

申请号：US14858347

申请日：2015-09-18

Applicant: INPHI CORPORATION

Inventor： Sheldon James Hood ,  Paul Thomas Banens

IPC: H04L7/00 ,  H03K5/135 ,  H04B1/04 ,  H03K5/00

CPC classification number: H04L7/0016 ,  H03K5/133 ,  H03K5/135 ,  H03K19/00361 ,  H03K19/21 ,  H03K2005/00078 ,  H03L7/0807 ,  H04B1/04 ,  H04L25/49

Abstract: When a data path includes CMOS circuitry, such circuitry may introduce jitter into the data signal. Embodiments are described in which additional data transitions are made to occur, and these additional data transitions may change the characteristics of the data frequency content transferred to the power supply so that such noise may be better filtered. This may have an effect of reducing jitter in the data signal. In one embodiment, a second data signal is generated to be a version of a first data signal with every second bit inverted. Second CMOS circuitry receives the second data signal in parallel to first CMOS circuitry receiving the first data signal. The first CMOS circuitry and the second CMOS circuitry are connected to a same power supply.

公开(公告)号：US09973329B2

公开(公告)日：2018-05-15

申请号：US15474593

申请日：2017-03-30

Applicant: INPHI CORPORATION

Inventor： Sheldon James Hood ,  Paul Thomas Banens

IPC: H04L7/00 ,  H04B1/04 ,  H03K19/21 ,  H03L7/08

CPC classification number: H04L7/0016 ,  H03K5/133 ,  H03K5/135 ,  H03K19/00361 ,  H03K19/21 ,  H03K2005/00078 ,  H03L7/0807 ,  H04B1/04 ,  H04L25/49

Abstract: When a data path includes CMOS circuitry, such circuitry may introduce jitter into the data signal. Embodiments are described in which additional data transitions are made to occur, and these additional data transitions may change the characteristics of the data frequency content transferred to the power supply so that such noise may be better filtered. This may have an effect of reducing jitter in the data signal. In one embodiment, a second data signal is generated to be a version of a first data signal with every second bit inverted. Second CMOS circuitry receives the second data signal in parallel to first CMOS circuitry receiving the first data signal. The first CMOS circuitry and the second CMOS circuitry are connected to a same power supply.