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    Full electronic two-wire to four-wire conversion circuit
    3.
    发明授权
    Full electronic two-wire to four-wire conversion circuit 失效
    全电子二线到四线转换电路

    公开(公告)号：US3886322A

    公开(公告)日：1975-05-27

    申请号：US29938572

    申请日：1972-10-20

    Applicant: INT STANDARD ELECTRIC CORP

    Inventor： COLARDELLE JOEL SERGE ,  GIRARD PIERRE ,  LEROUGE CLAUDE PAUL HENRI

    IPC: H04B1/58 ,  H04L25/22 ,  H04M19/00 ,  H04Q3/52

    CPC classification number: H04Q3/521 ,  H04B1/586 ,  H04L25/22 ,  H04M19/005

    Abstract: A circuit is disclosed for use in data switching wherein a twowire to four-wire conversion (''''hybrid'''' function) is performed by all-electronic means. These means comprise one complementary symmetry differential amplifier with emitter coupling per direction of transmission with adequate provision for minimizing interaction between both directions. Means are also provided for minimizing inter-line and inter-junctor crosstalk by supplying lines and junctors through active ''''gyrators'''' equivalent to series inductances.

    Abstract translation: 公开了一种用于数据交换的电路，其中通过全电子方式执行双线至四线转换（“混合”功能）。 这些装置包括一个互补对称差分放大器，每个传输方向具有发射极耦合，并具有足够的设置，以最小化双向交互。 还提供了用于通过相当于串联电感的主动“回转器”提供线路和接头来最小化线间和串联串扰的装置。

    Time division multiplex analog-digital or digital-analog converter
    5.
    发明授权
    Time division multiplex analog-digital or digital-analog converter 失效
    时分多模式数字或数字模拟转换器

    公开(公告)号：US3594765A

    公开(公告)日：1971-07-20

    申请号：US3594765D

    申请日：1968-12-26

    Applicant: INT STANDARD ELECTRIC CORP

    Inventor： LEROUGE CLAUDE PAUL HENRI ,  REGNIER MARC ANDRE ,  STRUBE DIDIER CHARLES

    IPC: H03M1/00 ,  H04J3/04 ,  H03K13/02

    CPC classification number: H04J3/04 ,  H03M1/00 ,  H03M1/50

    Abstract: A plurality of binary counters are provided, each of which are assigned to a different channel signal, and arranged in two groups. A timing signal source and logic circuitry associated with each counter cooperate to cause the counters of one group to convert the analog or digital signal of that group and simultaneously connect the counters of the other group in series and to function as shift registers to produce the serial output of previously coded analog signals or to store serial digital input codes. The function of the counters are then reversed. When functioning as analog-digital converters, the counters start counting and the analog signals are compared to a reference sawtooth waveform. When the amplitude of the analog signal equals the amplitude of the waveform, the counting is stopped and the code stored therein represents the amplitude of the analog signal. In the digital-analog converter, the counters of a group which store digital codes previously shifted into these counters start counting and cooperate with a bistable device to produce PWM pulses which is operated on to reproduce the analog signals.

    Encoder for wide band signals
    6.
    发明授权
    Encoder for wide band signals 失效
    ENCODER FOR WIDE BAND SIGNALS

    公开(公告)号：US3588876A

    公开(公告)日：1971-06-28

    申请号：US3588876D

    申请日：1967-09-07

    Applicant: INT STANDARD ELECTRIC CORP

    Inventor： CHATELON ANDRE EDOUARD JOSEPH ,  LEROUGE CLAUDE PAUL HENRI ,  LOUBOUTIN HERVE JEAN PIERRE MA

    IPC: H03M1/00 ,  H03K13/02

    CPC classification number: H03M1/56

    Abstract: M SAMPLE AND HOLD, AMPLITUDE COMPARISON AND LOGIC CIRCUITS ARE ACTIVATED BY TIMING SIGNALS DURING THE RISE TIME OF CYCLIC RAMP SIGNALS TO PRODUCE WRITE AND READ SIGNALS. EACH CIRCUIT PRODUCES A WRITE SIGNAL WHEN THE AMPLITUDES OF AN ANALOG SIGNAL AND ONE OF THE RAMP SIGNALS ARE EQUAL AND SIMULTANEOUSLY THE ASSOCIATED ONES OF THE TIMING SIGNALS ARE ABSENT IN THE RISE TIME OF SAID ONE OF SAID RAMP SIGNALS TO TRANSFER THE COUNT OF THE N LEAST SIGNIFICANT BINARY WEIGHTED STAGES OF AN (N+1) STAGE CODING COUNTER TO ASSOCIATED COLUMNS OF AN M-LINE, N-COLUMN MEMORY AND A READ SIGNAL WHEN THE ASSOCIATED ONES OF THE TIMING SIGNALS ARE PRESENT IN THE RISE TIME OF THE NEXT SUCCEEDING ONE OF SAID RAMP SIGNALS TO TRANSFER THE STORED CODE TO EXTERNAL CIRCUITS.

    Non-linear decoder with linear and non-linear ladder attenuators
    7.
    发明授权
    Non-linear decoder with linear and non-linear ladder attenuators 失效
    带线性和非线性梯形失真器的非线性解码器

    公开(公告)号：US3653033A

    公开(公告)日：1972-03-28

    申请号：US3653033D

    申请日：1969-06-23

    Applicant: INT STANDARD ELECTRIC CORP

    Inventor： BONAMI ROBERT RAOUL CHARLES ,  LEROUGE CLAUDE PAUL HENRI ,  STRUBE DIDIER CHARLES

    IPC: H03M1/00 ,  H03K13/04

    CPC classification number: H03M1/00 ,  H03M1/82

    Abstract: A PCM word decoder has a characteristic curve which is symmetrical with respect to zero abscissa point. Starting from the zero abscissa point, the curve comprises a linear part corresponding to the eight first codes, a logarithmic part corresponding to 40 following codes and a linear part corresponding to the 16 last codes. This is accomplished by two identical ladder attenuators and two sets of current generators. One attenuator and set of generators correspond to the logarithmic part, and the other to the linear part.

    Abstract translation: PCM字解码器具有相对于零横坐标点对称的特性曲线。 从零横坐标点开始，曲线包括对应于八个第一代码的线性部分，对应于40个跟随代码的对数部分和对应于16个最后代码的线性部分。 这是由两个相同的梯形衰减器和两组电流发生器完成的。 一个衰减器和一组发生器对应于对数部分，另一个对应于线性部分。

    Interface unit for a telephone exchange
    8.
    发明授权
    Interface unit for a telephone exchange 失效
    电话交换界面单元

    公开(公告)号：US3626105A

    公开(公告)日：1971-12-07

    申请号：US3626105D

    申请日：1969-06-23

    Applicant: INT STANDARD ELECTRIC CORP

    Inventor： JEAN JACQUES HENRI DE ,  LEGER MARC JEAN PIERRE ,  LEROUGE CLAUDE PAUL HENRI

    IPC: G06F13/22 ,  H04Q3/545 ,  H04Q3/54

    CPC classification number: G06F13/22 ,  H04Q3/5455 ,  H04Q3/54583 ,  H04Q2213/13057

    Abstract: An interface unit is provided for connection between each of a plurality of peripheral devices and a central processing unit. The peripheral devices include such things as subscribers lines, trunks and junctors. The interface unit includes a temporary memory for storing status information or instructions regarding the peripheral devices. A permanent memory delivers regulating signals for scanning current test inputs and comparing them with data stored in the temporary memory. When there is a discrepancy in the data in the memories, the unit calls the central processor and sends its information to the central processor, where it is processed and new data is sent back to the unit.

    Switching stage with mos crosspoints
    9.
    发明授权
    Switching stage with mos crosspoints 失效
    切换阶段与MOS CROSSPOINTS

    公开(公告)号：US3626104A

    公开(公告)日：1971-12-07

    申请号：US3626104D

    申请日：1969-06-19

    Applicant: INT STANDARD ELECTRIC CORP

    Inventor： LEGER MARC JEAN PIERRE ,  LEROUGE CLAUDE PAUL HENRI ,  REGNIER MARC ANDRE

    IPC: H04Q3/52 ,  H04Q3/00

    CPC classification number: H04Q3/521

    Abstract: A switching stage is provided which employs multiselectors formed by MOS crosspoints. The operations of path search, subscriber test and call detection are made by a cyclic exploration of all the possible paths between a junctor and one (or all) subscriber(s). The supervision data (''''off-hook'''' condition and ''''path established'''' condition) are obtained by monitoring the DC levels on the two speech conductors.

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