Fault locating system for a transmission line having a plurality of repeaters including a detector coupled to the output of each repeater
    3.
    发明授权
    Fault locating system for a transmission line having a plurality of repeaters including a detector coupled to the output of each repeater 失效
    用于具有多个重复器的传输线的故障定位系统,包括与每个重复器的输出耦合的检测器

    公开(公告)号:US3586968A

    公开(公告)日:1971-06-22

    申请号:US3586968D

    申请日:1969-03-06

    CPC classification number: H04J3/14 H04B17/408

    Abstract: In a PCM communication system including a transmission line having a plurality of repeaters therealong, one at the end of each section of the line, a fault is located as follows. A repetitive code having a fundamental frequency F is propagated over the line from a transmitting station. A different detector responsive to frequency F is coupled to the output of each repeater. Each of the detectors is coupled to a different pulse generator. The pulse generators, before a fault responds to the detected frequency F to generate rectangular pulses having a given amplitude and a frequency F. These pulses are coupled to a supervisory transmission line without repeaters. At the receiving station measuring equipment detects the amplitude of the rectangular pulses on the supervisory line. The detected amplitude locates the fault. Where the communication system includes a plurality of main transmission lines, each pulse generator is common to the repeaters of a corresponding section of each of the main lines.

    Full electronic two-wire to four-wire conversion circuit
    4.
    发明授权
    Full electronic two-wire to four-wire conversion circuit 失效
    全电子二线到四线转换电路

    公开(公告)号:US3886322A

    公开(公告)日:1975-05-27

    申请号:US29938572

    申请日:1972-10-20

    CPC classification number: H04Q3/521 H04B1/586 H04L25/22 H04M19/005

    Abstract: A circuit is disclosed for use in data switching wherein a twowire to four-wire conversion (''''hybrid'''' function) is performed by all-electronic means. These means comprise one complementary symmetry differential amplifier with emitter coupling per direction of transmission with adequate provision for minimizing interaction between both directions. Means are also provided for minimizing inter-line and inter-junctor crosstalk by supplying lines and junctors through active ''''gyrators'''' equivalent to series inductances.

    Abstract translation: 公开了一种用于数据交换的电路,其中通过全电子方式执行双线至四线转换(“混合”功能)。 这些装置包括一个互补对称差分放大器,每个传输方向具有发射极耦合,并具有足够的设置,以最小化双向交互。 还提供了用于通过相当于串联电感的主动“回转器”提供线路和接头来最小化线间和串联串扰的装置。

    Two-wire to four-wire conversion circuit for a data switching center
    5.
    发明授权
    Two-wire to four-wire conversion circuit for a data switching center 失效
    用于数据切换中心的四线转换电路

    公开(公告)号:US3689710A

    公开(公告)日:1972-09-05

    申请号:US3689710D

    申请日:1970-10-12

    CPC classification number: H04B1/581 H04B1/586 H04Q3/521

    Abstract: In a two-wire to four-wire data switching center, the usual hybrid transformer(s) is replaced by a single transformer with a symmetrical secondary. Interaction between both directions of transmission is avoided by connecting the extremities of the secondary respectively to the output of a first current amplifier and to the input of a second current amplifier. This circuit is intended specifically for use with electronic switching such as that using MOS switching crosspoints and stages.

    Abstract translation: 在二线到四线数据交换中心,通常的混合变压器由具有对称次级的单个变压器代替。 通过将次级的四极分别连接到第一电流放大器的输出和第二电流放大器的输入来避免传输的两个方向之间的相互作用。 该电路专门用于电子开关,例如使用MOS开关交叉点和级的电路。

    Non-linear digital to analog decoder with a smooth characteristic
    6.
    发明授权
    Non-linear digital to analog decoder with a smooth characteristic 失效
    非线性数字到具有平滑特性的模拟解码器

    公开(公告)号:US3579232A

    公开(公告)日:1971-05-18

    申请号:US3579232D

    申请日:1969-04-23

    CPC classification number: H04B14/048 H03M1/00 H03M1/50

    Abstract: A digital to analog decoder or converter is disclosed. The decoder has a smooth nonlinear characteristic of the hyperbolic sine type. This smooth characteristic is contrasted to a nonlinear characteristic approximated by a plurality of straight line segments in the prior art. The decoder of this case includes a register to store a 7-digit code to be decoded. A first decoder circuit decodes the last four digits of the 7-digit code. Two groups of current generators (a first selection circuit) responding to the output of the first decoder produce two currents. A bipolar inverter (a second selection circuit) responding to the first of the last four digits directs the two currents to a third selection circuit. The third selection circuit responds to the output of of a second decoder to direct the two currents to the appropriate one of two ladder attenuators, the outputs of which produce the analog signal. The second decoder responds to the first three digits of the 7-digit code.

Patent Agency Ranking