公开(公告)号：US20170286349A1

公开(公告)日：2017-10-05

申请号：US15088157

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Samantha J. Edirisooriya ,  Roger C. Jeppsen ,  Pankaj Kumar ,  Blaine R. Monson

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4081 ,  G06F13/4282

Abstract: Method, apparatus, and system of detecting a hot-plug event. The hot-plug event detection may be done in-band or out-of-band. The in-band detection is performed by a state machine and the out-of-band detection is performed by a logic. A circuitry is to detect a hot-plug event when inserting or removing a device from an extension bus of the plurality of extension bus slots. The circuit is to generate a hot-plug message to notify the hot-plug event. The circuitry including the state machine, the logic and a register to provide at least two bits to mask at least two states of the state machine.

公开(公告)号：US09953001B2

公开(公告)日：2018-04-24

申请号：US15088157

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Samantha J. Edirisooriya ,  Roger C. Jeppsen ,  Pankaj Kumar ,  Blaine R. Monson

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4081 ,  G06F13/4282

Abstract: Method, apparatus, and system of detecting a hot-plug event. The hot-plug event detection may be done in-band or out-of-band. The in-band detection is performed by a state machine and the out-of-band detection is performed by a logic. A circuitry is to detect a hot-plug event when inserting or removing a device from an extension bus of the plurality of extension bus slots. The circuit is to generate a hot-plug message to notify the hot-plug event. The circuitry including the state machine, the logic and a register to provide at least two bits to mask at least two states of the state machine.

公开(公告)号：US20170040051A1

公开(公告)日：2017-02-09

申请号：US14816445

申请日：2015-08-03

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Shanker R. Nagesh ,  K L Siva Prasad Gadey N V ,  Blaine R. Monson ,  Pankaj Kumar

IPC: G11C11/406 ,  G06F1/26 ,  G06F1/28 ,  G11C7/10 ,  G06F13/38

CPC classification number: G11C11/40622 ,  G06F1/263 ,  G06F1/28 ,  G06F1/30 ,  G06F13/385 ,  G11C7/1072 ,  G11C11/40615 ,  G11C2211/4067 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.

Abstract translation: 在一个实施例中，一种装置包括处理器核心和功率控制单元。 功率控制单元用于识别来自主电源的功率损耗的发生，指示I / O控制器阻止来自一个或多个I / O设备的进一步写入请求，并发送至少一个待写入请求， I / O控制器到存储器控制器，并且指示存储器控制器完成由存储器控制器存储的至少一个未决写入请求并使存储器被置于自刷新模式。

公开(公告)号：US10679690B2

公开(公告)日：2020-06-09

申请号：US16185374

申请日：2018-11-09

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Shanker R. Nagesh ,  K L Siva Prasad Gadey N V ,  Blaine R. Monson ,  Pankaj Kumar

IPC: G11C11/406 ,  G11C7/10 ,  G06F13/38 ,  G06F1/28 ,  G06F1/26 ,  G06F1/30

Abstract: In one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.

公开(公告)号：US10127968B2

公开(公告)日：2018-11-13

申请号：US14816445

申请日：2015-08-03

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Shanker R. Nagesh ,  K L Siva Prasad Gadey N V ,  Blaine R. Monson ,  Pankaj Kumar

IPC: G11C11/406 ,  G11C7/10 ,  G06F13/38 ,  G06F1/28 ,  G06F1/26 ,  G06F1/30

Abstract: In one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.

公开(公告)号：US20190147938A1

公开(公告)日：2019-05-16

申请号：US16185374

申请日：2018-11-09

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Shanker R. Nagesh ,  K L Siva Prasad Gadey N V ,  Blaine R. Monson ,  Pankaj Kumar

IPC: G11C11/406 ,  G06F1/28 ,  G06F1/26 ,  G06F1/30 ,  G11C7/10 ,  G06F13/38

Abstract: In one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.

公开(公告)号：US20180352679A1

公开(公告)日：2018-12-06

申请号：US15612093

申请日：2017-06-02

Applicant: Intel Corporation

Inventor： Blaine R. Monson ,  Pankaj Kumar ,  Anthony K. Wong ,  Uzair A. Qureshi

IPC: H05K7/20 ,  H05K7/14

Abstract: A memory device carrier is described that is particular suitable for a high density rack drive chassis in which the drives are front serviceable. In one example, a memory system includes an enclosure configured to mount in a rack, the enclosure having a front configured to receive airflow and a rear configured for cabling, a drawer configured to slide longitudinally in and out of the enclosure, the drawer having a bottom surface and a front face, and a longitudinal connector board mounted to the drawer having a plurality of memory device sockets, the sockets facing outward laterally from the longitudinal board and configured to receive memory devices inserted laterally into a respective socket.