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公开(公告)号：US20190179786A1
公开(公告)日：2019-06-13
申请号：US16279485
申请日：2019-02-19
Applicant: Intel Corporation
Inventor： Samantha J. Edirisooriya , Geetani R. Edirisooriya , Roger C. Jeppsen , Pankaj Kumar
Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.
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公开(公告)号：US09983660B2
公开(公告)日：2018-05-29
申请号：US14974064
申请日：2015-12-18
Applicant: Intel Corporation
Inventor： Pankaj Kumar , Hang T. Nguyen , Christopher Houghton , David A. Biermann
CPC classification number: G06F1/3296 , G05F1/46 , G06F1/26 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F9/3016 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.
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公开(公告)号：US09983659B2
公开(公告)日：2018-05-29
申请号：US14966273
申请日：2015-12-11
Applicant: Intel Corporation
Inventor： Pankaj Kumar , Hang T. Nguyen , Christopher Houghton , David A. Biermann
CPC classification number: G06F1/3296 , G05F1/46 , G06F1/26 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F9/3016 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.
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公开(公告)号：US20170286349A1
公开(公告)日：2017-10-05
申请号：US15088157
申请日：2016-04-01
Applicant: INTEL CORPORATION
Inventor： Samantha J. Edirisooriya , Roger C. Jeppsen , Pankaj Kumar , Blaine R. Monson
CPC classification number: G06F13/4081 , G06F13/4282
Abstract: Method, apparatus, and system of detecting a hot-plug event. The hot-plug event detection may be done in-band or out-of-band. The in-band detection is performed by a state machine and the out-of-band detection is performed by a logic. A circuitry is to detect a hot-plug event when inserting or removing a device from an extension bus of the plurality of extension bus slots. The circuit is to generate a hot-plug message to notify the hot-plug event. The circuitry including the state machine, the logic and a register to provide at least two bits to mask at least two states of the state machine.
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公开(公告)号：US09348387B2
公开(公告)日：2016-05-24
申请号：US14570100
申请日：2014-12-15
Applicant: Intel Corporation
Inventor： Pankaj Kumar , Hang T. Nguyen , Christopher Houghton , David A. Biermann
CPC classification number: G06F1/3296 , G05F1/46 , G06F1/26 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F9/3016 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US20160098079A1
公开(公告)日：2016-04-07
申请号：US14966286
申请日：2015-12-11
Applicant: Intel Corporation
Inventor： Pankaj Kumar , Hang T. Nguyen , Christopher Houghton , David A. Biermann
IPC: G06F1/32
CPC classification number: G06F1/3296 , G05F1/46 , G06F1/26 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F9/3016 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.
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公开(公告)号：US11449446B2
公开(公告)日：2022-09-20
申请号：US16936078
申请日：2020-07-22
Applicant: Intel Corporation
Inventor： Thomas M. Slaight , Sivakumar Radhakrishnan , Mark Schmisseur , Pankaj Kumar , Saptarshi Mondal , Sin S. Tan , David C. Lee , Marc T. Jones , Geetani R. Edirisooriya , Bradley A. Burres , Brian M. Leitner , Kenneth C. Haren , Michael T. Klinglesmith , Matthew R. Wilcox , Eric J. Dahlen
Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.
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公开(公告)号：US20160335208A1
公开(公告)日：2016-11-17
申请号：US15224006
申请日：2016-07-29
Applicant: Intel Corporation
Inventor： Thomas M. Slaight , Sivakumar Radhakrishnan , Mark Schmisseur , Pankaj Kumar , Saptarshi Mondal , Sin S. Tan , David C. Lee , Marc T. Jones , Geetani R. Edirisooriya , Bradley A. Burres , Brian M. Leitner , Kenneth C. Haren , Michael T. Klinglesmith , Matthew R. Wilcox , Eric J. Dahlen
CPC classification number: G06F13/28 , G06F3/0607 , G06F3/061 , G06F3/0613 , G06F3/0619 , G06F3/0626 , G06F3/064 , G06F3/0646 , G06F3/065 , G06F3/0659 , G06F3/0661 , G06F3/0673 , G06F3/0688 , G06F3/0689 , G06F11/1068 , G06F12/0866 , G06F13/102 , G06F13/1668 , G06F13/4068 , G06F13/4282 , G06F2212/262 , G06F2213/0026 , G06F2213/0032
Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme. For instance, there is disclosed a storage apparatus having therein a plurality of NAND (Negated AND) based flash memory components arranged into a plurality of NAND arrays; a NAND controller communicatively interfaced with the plurality of NAND arrays; and block mirroring logic to establish a mirrored copy for each data block written to the storage apparatus, each mirrored copy to be stored within one of plurality of NAND arrays. Other related embodiments are disclosed.
Abstract translation: 根据本文公开的实施例，提供了用于在逻辑驱动器模型下呈现直接访问存储的方法，系统，机制，技术和装置; 实现用于协作NVM数据保护的分布式架构; 数据镜像，以保持一致的SSD延迟; 通过并发RAID处理来提升控制器的性能和支持DIF的RAS; 执行门铃机制的仲裁和资源计划，包括门铃仲裁以公平和防止冲突拥堵; 并且通过使用中断合并方案在控制器中实现使用消息传送单元和NTB的多个中断生成。 例如，公开了一种存储装置，其中具有排列成多个NAND阵列的多个基于NAND（Negated AND）的闪速存储器组件; 与多个NAND阵列通信地对接的NAND控制器; 和块镜像逻辑，以便为写入存储设备的每个数据块建立镜像拷贝，每个镜像拷贝存储在多个NAND阵列之一内。 公开了其他相关实施例。
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公开(公告)号：US20160098078A1
公开(公告)日：2016-04-07
申请号：US14966273
申请日：2015-12-11
Applicant: Intel Corporation
Inventor： Pankaj Kumar , Hang T. Nguyen , Christopher Houghton , David A. Biermann
IPC: G06F1/32
CPC classification number: G06F1/3296 , G05F1/46 , G06F1/26 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F9/3016 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.
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公开(公告)号：US20150143139A1
公开(公告)日：2015-05-21
申请号：US14570100
申请日：2014-12-15
Applicant: Intel Corporation
Inventor： Pankaj Kumar , Hang T. Nguyen , Christopher Houghton , David A. Biermann
CPC classification number: G06F1/3296 , G05F1/46 , G06F1/26 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F9/3016 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有多个核心的处理器和用于控制向多个核心的第一核心提供电压/频率的控制逻辑，而不管将电压/频率提供给至少第二核心 的多个核心。 在一些实施例中，可以从处理器的一个或多个内部稳压器提供电压。 描述和要求保护其他实施例。
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