公开(公告)号：US20190147938A1

公开(公告)日：2019-05-16

申请号：US16185374

申请日：2018-11-09

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Shanker R. Nagesh ,  K L Siva Prasad Gadey N V ,  Blaine R. Monson ,  Pankaj Kumar

IPC: G11C11/406 ,  G06F1/28 ,  G06F1/26 ,  G06F1/30 ,  G11C7/10 ,  G06F13/38

Abstract: In one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.

公开(公告)号：US20190179786A1

公开(公告)日：2019-06-13

申请号：US16279485

申请日：2019-02-19

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Geetani R. Edirisooriya ,  Roger C. Jeppsen ,  Pankaj Kumar

IPC: G06F13/28 ,  G06F9/54 ,  G06F13/40 ,  G06F9/455 ,  G06F13/10

Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.

公开(公告)号：US10235302B2

公开(公告)日：2019-03-19

申请号：US15375582

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Geetani R. Edirisooriya

IPC: G06F12/128 ,  G06F12/0808

Abstract: In an embodiment, a processor for invalidating cache entries comprises: at least one processing unit; a processor cache; and direct cache unit. The direct cache unit is to receive, from a first device, a direct read request for data in a first cache entry in the processor cache; determine whether the direct read request is an invalidating read request; in response to a determination that the direct read request is an invalidating read request: send the data in the first cache entry directly from the processor cache to the first device without accessing a main memory; and invalidate the first cache entry in the processor cache. Other embodiments are described and claimed.

公开(公告)号：US20170286349A1

公开(公告)日：2017-10-05

申请号：US15088157

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Samantha J. Edirisooriya ,  Roger C. Jeppsen ,  Pankaj Kumar ,  Blaine R. Monson

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4081 ,  G06F13/4282

Abstract: Method, apparatus, and system of detecting a hot-plug event. The hot-plug event detection may be done in-band or out-of-band. The in-band detection is performed by a state machine and the out-of-band detection is performed by a logic. A circuitry is to detect a hot-plug event when inserting or removing a device from an extension bus of the plurality of extension bus slots. The circuit is to generate a hot-plug message to notify the hot-plug event. The circuitry including the state machine, the logic and a register to provide at least two bits to mask at least two states of the state machine.

公开(公告)号：US10990546B2

公开(公告)日：2021-04-27

申请号：US16279485

申请日：2019-02-19

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Geetani R. Edirisooriya ,  Roger C. Jeppsen ,  Pankaj Kumar

IPC: G06F13/28 ,  G06F9/455 ,  G06F13/10 ,  G06F13/40 ,  G06F9/54

Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.

公开(公告)号：US10679690B2

公开(公告)日：2020-06-09

申请号：US16185374

申请日：2018-11-09

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Shanker R. Nagesh ,  K L Siva Prasad Gadey N V ,  Blaine R. Monson ,  Pankaj Kumar

IPC: G11C11/406 ,  G11C7/10 ,  G06F13/38 ,  G06F1/28 ,  G06F1/26 ,  G06F1/30

Abstract: In one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.

公开(公告)号：US10127968B2

公开(公告)日：2018-11-13

申请号：US14816445

申请日：2015-08-03

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Shanker R. Nagesh ,  K L Siva Prasad Gadey N V ,  Blaine R. Monson ,  Pankaj Kumar

IPC: G11C11/406 ,  G11C7/10 ,  G06F13/38 ,  G06F1/28 ,  G06F1/26 ,  G06F1/30

Abstract: In one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.

公开(公告)号：US20180225237A1

公开(公告)日：2018-08-09

申请号：US15423949

申请日：2017-02-03

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Geetani R. Edirisooriya ,  Roger C. Jeppsen ,  Pankaj Kumar

IPC: G06F13/28 ,  G06F9/455 ,  G06F13/10 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F9/45533 ,  G06F9/54 ,  G06F13/102 ,  G06F13/4068 ,  G06F2213/0026

Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.

公开(公告)号：US10241947B2

公开(公告)日：2019-03-26

申请号：US15423949

申请日：2017-02-03

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Geetani R. Edirisooriya ,  Roger C. Jeppsen ,  Pankaj Kumar

IPC: G06F13/28 ,  G06F9/455 ,  G06F13/10 ,  G06F13/40 ,  G06F9/54

Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.

公开(公告)号：US09953001B2

公开(公告)日：2018-04-24

申请号：US15088157

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Samantha J. Edirisooriya ,  Roger C. Jeppsen ,  Pankaj Kumar ,  Blaine R. Monson

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4081 ,  G06F13/4282

Abstract: Method, apparatus, and system of detecting a hot-plug event. The hot-plug event detection may be done in-band or out-of-band. The in-band detection is performed by a state machine and the out-of-band detection is performed by a logic. A circuitry is to detect a hot-plug event when inserting or removing a device from an extension bus of the plurality of extension bus slots. The circuit is to generate a hot-plug message to notify the hot-plug event. The circuitry including the state machine, the logic and a register to provide at least two bits to mask at least two states of the state machine.