公开(公告)号：US20190042944A1

公开(公告)日：2019-02-07

申请号：US16004243

申请日：2018-06-08

Applicant: Intel Corporation

Inventor： Krishnakumar Nair ,  Andrew Yang ,  Brian Morris

IPC: G06N3/08 ,  G06N3/04

Abstract: Thus, the present disclosure is directed to systems and methods for training neural networks using a tensor that includes a plurality of FP16 values and a plurality of bits that define an exponent shared by some or all of the FP16 values included in the tensor. The FP16 values may include IEEE 754 format 16-bit floating point values and the tensor may include a plurality of bits defining the shared exponent. The tensor may include a shared exponent and FP16 values that include a variable bit-length mantissa and a variable bit-length exponent that may be dynamically set by processor circuitry. The tensor may include a shared exponent and FP16 values that include a variable bit-length mantissa; a variable bit-length exponent that may be dynamically set by processor circuitry; and a shared exponent switch set by the processor circuitry to selectively combine the FP16 value exponent with the shared exponent.

公开(公告)号：US10762244B2

公开(公告)日：2020-09-01

申请号：US16024022

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Joshua Fender ,  Utkarsh Y. Kakaiya ,  Mohan Nair ,  Brian Morris ,  Pratik Marolia

IPC: G06F21/00 ,  G06F21/76 ,  H04L29/08 ,  G06F11/14 ,  G06F1/3206 ,  G06F21/54 ,  G06F1/324 ,  G06F21/74 ,  H04L29/06 ,  G06F1/20 ,  G06F1/3287

Abstract: Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.

公开(公告)号：US12205035B2

公开(公告)日：2025-01-21

申请号：US16004243

申请日：2018-06-08

Applicant: Intel Corporation

Inventor： Krishnakumar Nair ,  Andrew Yang ,  Brian Morris

IPC: G06N3/084 ,  G06F9/30 ,  G06N3/045 ,  G06N3/063

Abstract: Thus, the present disclosure is directed to systems and methods for training neural networks using a tensor that includes a plurality of FP16 values and a plurality of bits that define an exponent shared by some or all of the FP16 values included in the tensor. The FP16 values may include IEEE 754 format 16-bit floating point values and the tensor may include a plurality of bits defining the shared exponent. The tensor may include a shared exponent and FP16 values that include a variable bit-length mantissa and a variable bit-length exponent that may be dynamically set by processor circuitry. The tensor may include a shared exponent and FP16 values that include a variable bit-length mantissa; a variable bit-length exponent that may be dynamically set by processor circuitry; and a shared exponent switch set by the processor circuitry to selectively combine the FP16 value exponent with the shared exponent.

公开(公告)号：US20240028905A1

公开(公告)日：2024-01-25

申请号：US18478554

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Krishnakumar Nair ,  Andrew Yang ,  Brian Morris

IPC: G06N3/084 ,  G06N3/063 ,  G06N3/045

CPC classification number: G06N3/084 ,  G06N3/063 ,  G06N3/045 ,  G06F9/3013

Abstract: Thus, the present disclosure is directed to systems and methods for training neural networks using a tensor that includes a plurality of FP16 values and a plurality of bits that define an exponent shared by some or all of the FP16 values included in the tensor. The FP16 values may include IEEE 754 format 16-bit floating point values and the tensor may include a plurality of bits defining the shared exponent. The tensor may include a shared exponent and FP16 values that include a variable bit-length mantissa and a variable bit-length exponent that may be dynamically set by processor circuitry. The tensor may include a shared exponent and FP16 values that include a variable bit-length mantissa; a variable bit-length exponent that may be dynamically set by processor circuitry; and a shared exponent switch set by the processor circuitry to selectively combine the FP16 value exponent with the shared exponent.