公开(公告)号：US10762244B2

公开(公告)日：2020-09-01

申请号：US16024022

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Joshua Fender ,  Utkarsh Y. Kakaiya ,  Mohan Nair ,  Brian Morris ,  Pratik Marolia

IPC: G06F21/00 ,  G06F21/76 ,  H04L29/08 ,  G06F11/14 ,  G06F1/3206 ,  G06F21/54 ,  G06F1/324 ,  G06F21/74 ,  H04L29/06 ,  G06F1/20 ,  G06F1/3287

Abstract: Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.

公开(公告)号：US12197887B2

公开(公告)日：2025-01-14

申请号：US16818889

申请日：2020-03-13

Applicant: Intel Corporation

Inventor： Roberto DiCecco ,  Joshua Fender ,  Shane O'Connell

IPC: G06F7/485 ,  G06F7/483 ,  G06F7/487 ,  G06F7/499 ,  G06F7/544 ,  G06F17/16

Abstract: Circuitry for decomposing block floating-point numbers into lower precision floating-point numbers is provided. The circuitry may include a high precision storage circuit configured to provide high precision floating-point numbers, input selectors configured to receive the high precision floating-point numbers from the high precision storage circuit and to generate corresponding lower precision floating-point components with adjusted exponents, and a low precision block floating-point vector circuit configured to combine the various lower precision floating-point components generated by the input selectors. The lower precision floating-point components may be processed spatially or over multiple iterations over time.

公开(公告)号：US20240126506A1

公开(公告)日：2024-04-18

申请号：US18399381

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Roberto DiCecco ,  Joshua Fender ,  Shane O'Connell

IPC: G06F7/485 ,  G06F7/483 ,  G06F7/487 ,  G06F7/499 ,  G06F7/544 ,  G06F17/16

CPC classification number: G06F7/485 ,  G06F7/483 ,  G06F7/4876 ,  G06F7/49947 ,  G06F7/5443 ,  G06F17/16

Abstract: Circuitry for decomposing block floating-point numbers into lower precision floating-point numbers is provided. The circuitry may include a high precision storage circuit configured to provide high precision floating-point numbers, input selectors configured to receive the high precision floating-point numbers from the high precision storage circuit and to generate corresponding lower precision floating-point components with adjusted exponents, and a low precision block floating-point vector circuit configured to combine the various lower precision floating-point components generated by the input selectors. The lower precision floating-point components may be processed spatially or over multiple iterations over time.

公开(公告)号：US20200218508A1

公开(公告)日：2020-07-09

申请号：US16818889

申请日：2020-03-13

Applicant: Intel Corporation

Inventor： Roberto DiCecco ,  Joshua Fender ,  Shane O'Connell

IPC: G06F7/485 ,  G06F7/487 ,  G06F7/544 ,  G06F7/499 ,  G06F9/30 ,  G06F17/16

Abstract: Circuitry for decomposing block floating-point numbers into lower precision floating-point numbers is provided. The circuitry may include a high precision storage circuit configured to provide high precision floating-point numbers, input selectors configured to receive the high precision floating-point numbers from the high precision storage circuit and to generate corresponding lower precision floating-point components with adjusted exponents, and a low precision block floating-point vector circuit configured to combine the various lower precision floating-point components generated by the input selectors. The lower precision floating-point components may be processed spatially or over multiple iterations over time.