公开(公告)号：US20160187958A1

公开(公告)日：2016-06-30

申请号：US14582993

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： REN WANG ,  CHRISTIAN MACIOCCO ,  PATRICK CONNOR ,  DINESH KUMAR ,  NRUPAL JANI ,  DANIEL DAHLE ,  SAMEH GOBRIEL

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F1/3287 ,  G06F1/3278 ,  G06F13/4022 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to create an idle period for a processing unit and a switching circuit by buffering one or more packets in a buffer for one or more input/output (I/O) ports. Embodiments may include causing the processing unit and/or the switching circuit to operate in a lower power state during the idle period and causing the processing unit and/or the switching circuit to exit the lower power state by communicating one or more out-of-band messages to the processing unit and/or the switching circuit.

Abstract translation: 各种实施例通常涉及通过缓冲一个或多个输入/输出（I / O）端口的缓冲器中的一个或多个分组来为处理单元和切换电路创建空闲周期的装置，方法和其他技术。 实施例可以包括使得处理单元和/或开关电路在空闲周期期间以较低功率状态工作，并且使处理单元和/或开关电路通过传送一个或多个外部电源而退出低功率状态， 频带消息到处理单元和/或开关电路。