公开(公告)号：US20160182177A1

公开(公告)日：2016-06-23

申请号：US14582075

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： IRA WEINY ,  STEVEN R. CARBONARI ,  ALEXANDER W. MIN ,  TSUNG-YUAN C. TAI ,  BRIAN J. SKERRY ,  PATRICK CONNOR

IPC: H04J3/06 ,  H04L12/24 ,  H04L12/851 ,  H04L12/947 ,  H04L12/46

CPC classification number: H04J3/0661 ,  H04L12/4641 ,  H04L45/023 ,  H04L47/28 ,  H04L49/25 ,  H04L67/325 ,  H04L67/34

Abstract: Examples may include techniques to enable synchronized execution of a command by nodes in a network fabric. A node capable of hosting a fabric manager for the network fabric (fabric manager node) may generate one or more packets including a command to be executed by at least some nodes in the network fabric. In some examples, a time stamp is also included with at least one of the one or more packets to indicate to receiving nodes to execute the command at a synchronized time.

Abstract translation: 示例可以包括使网络结构中的节点能够同步执行命令的技术。 能够承载网络结构（结构管理器节点）的结构管理器的节点可以生成包括由网络结构中的至少一些节点执行的命令的一个或多个分组。 在一些示例中，时间戳还包括在一个或多个分组中的至少一个分组中，以指示接收节点在同步的时间执行命令。

公开(公告)号：US20160187958A1

公开(公告)日：2016-06-30

申请号：US14582993

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： REN WANG ,  CHRISTIAN MACIOCCO ,  PATRICK CONNOR ,  DINESH KUMAR ,  NRUPAL JANI ,  DANIEL DAHLE ,  SAMEH GOBRIEL

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F1/3287 ,  G06F1/3278 ,  G06F13/4022 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to create an idle period for a processing unit and a switching circuit by buffering one or more packets in a buffer for one or more input/output (I/O) ports. Embodiments may include causing the processing unit and/or the switching circuit to operate in a lower power state during the idle period and causing the processing unit and/or the switching circuit to exit the lower power state by communicating one or more out-of-band messages to the processing unit and/or the switching circuit.

Abstract translation: 各种实施例通常涉及通过缓冲一个或多个输入/输出（I / O）端口的缓冲器中的一个或多个分组来为处理单元和切换电路创建空闲周期的装置，方法和其他技术。 实施例可以包括使得处理单元和/或开关电路在空闲周期期间以较低功率状态工作，并且使处理单元和/或开关电路通过传送一个或多个外部电源而退出低功率状态， 频带消息到处理单元和/或开关电路。

公开(公告)号：US20160179582A1

公开(公告)日：2016-06-23

申请号：US14582084

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： BRIAN J. SKERRY ,  IRA WEINY ,  PATRICK CONNOR ,  TSUNG-YUAN C. TAI ,  ALEXANDER W. MIN

IPC: G06F9/50 ,  G06F9/455

CPC classification number: G06F9/5077 ,  G06F9/45558 ,  G06F9/5027 ,  G06F2009/45591 ,  G06F2209/5011 ,  Y02D10/22 ,  Y02D10/36

Abstract: Examples may include techniques to provide performance optimizing of service chains to reduce bottlenecks and/or increase efficiency. Information for performance of virtual elements of a service chain implemented using a shared pool of configurable computing resources may be received. The resource allocation of portions of the configurable computing resources supporting virtual elements of the service chain can be adjusted based on the received information.

Abstract translation: 示例可以包括提供服务链的性能优化以减少瓶颈和/或提高效率的技术。 可以接收用于使用共享的可配置计算资源池实现的服务链的虚拟元素的性能的信息。 可以基于所接收的信息来调整支持服务链的虚拟元素的可配置计算资源的部分的资源分配。