公开(公告)号：US20190116129A1

公开(公告)日：2019-04-18

申请号：US16218262

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： REN WANG ,  AHMAD A. SAMIH ,  CHRISTIAN MACIOCCO ,  ANDREW BROWN ,  TSUNG-YUAN C. TAI

IPC: H04L12/927 ,  H04L12/725 ,  H04L12/931 ,  H04L12/24 ,  H04L12/851 ,  H04L12/841 ,  H04L12/863

Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for routing data packets in a quality of service (QoS) enabled content-based network or interconnect fabric. Various embodiments describe how to manage data flow based on content-based attribute vectors (AVs) indicating QoS requirements with respect to the data packets in networking or platform interconnects. A dynamic scheduling based on AV information may improve trafficking efficiency and optimize system performance.

公开(公告)号：US20180109460A1

公开(公告)日：2018-04-19

申请号：US15473413

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： BYRON MAROHN ,  CHRISTIAN MACIOCCO ,  SAMEH GOBRIEL ,  REN WANG ,  TSUNG-YUAN C. TAI

IPC: H04L12/819 ,  H04L12/743

CPC classification number: H04L47/215 ,  H04L45/38 ,  H04L45/54 ,  H04L45/7453

Abstract: The present disclosure describes a process and apparatus for improving insertions of entries into a hash table. A large number of smaller virtual buckets may be combined together and associated with buckets used for hash table entry lookups and/or entry insertion. On insertion of an entry, hash table entries associated with a hashed-to virtual bucket may be moved between groups of buckets associated with the virtual bucket, to better distribute entries across the available buckets to reduce the number of entries in the largest buckets and the standard deviation of the bucket sizes across the entire hash table.

公开(公告)号：US20160187958A1

公开(公告)日：2016-06-30

申请号：US14582993

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： REN WANG ,  CHRISTIAN MACIOCCO ,  PATRICK CONNOR ,  DINESH KUMAR ,  NRUPAL JANI ,  DANIEL DAHLE ,  SAMEH GOBRIEL

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F1/3287 ,  G06F1/3278 ,  G06F13/4022 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to create an idle period for a processing unit and a switching circuit by buffering one or more packets in a buffer for one or more input/output (I/O) ports. Embodiments may include causing the processing unit and/or the switching circuit to operate in a lower power state during the idle period and causing the processing unit and/or the switching circuit to exit the lower power state by communicating one or more out-of-band messages to the processing unit and/or the switching circuit.

Abstract translation: 各种实施例通常涉及通过缓冲一个或多个输入/输出（I / O）端口的缓冲器中的一个或多个分组来为处理单元和切换电路创建空闲周期的装置，方法和其他技术。 实施例可以包括使得处理单元和/或开关电路在空闲周期期间以较低功率状态工作，并且使处理单元和/或开关电路通过传送一个或多个外部电源而退出低功率状态， 频带消息到处理单元和/或开关电路。