公开(公告)号：US20150188033A1

公开(公告)日：2015-07-02

申请号：US14140758

申请日：2013-12-26

Applicant: INTEL CORPORATION

Inventor： Daniel R. LAMBORN ,  Oleg Golonzka ,  Christopher Wiegand

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08

CPC classification number: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Methods of forming a memory device structure are described. Those methods may include forming a non-conductive spacer material on a top electrode of a magnetic tunnel junction structure, and then forming a highly selective material on the non-conductive spacer material of the magnetic tunnel junction prior to etching a bottom electrode of the magnetic tunnel junction.

Abstract translation: 描述形成存储器件结构的方法。 这些方法可以包括在磁性隧道结结构的顶部电极上形成非导电间隔物材料，然后在蚀刻磁性体的底部电极之前在磁性隧道结的非导电间隔物材料上形成高选择性材料 隧道交界处。

公开(公告)号：US20220148971A1

公开(公告)日：2022-05-12

申请号：US17441217

申请日：2019-05-09

Applicant: Intel Corporation

Inventor： Daniel R. LAMBORN ,  Chuan SUN ,  Qi ZHOU

IPC: H01L23/535 ,  H01L23/528 ,  H01L21/768

Abstract: Etch stops are disclosed for integrated circuit applications that have a set contacts of varying height, wherein there is a large height differential between the shortest and tallest contacts. In one example, an etch stop is provisioned over a 3D NAND memory staircase structure. The structure is then planarized with an insulator material that can be selectively etched with respect to the etch stop. Contact holes that land on corresponding wordlines of the staircase are etched. Due to the nature of the staircase, the holes vary in depth depending on which step of the staircase they land. The etch stop under the shallowest hole remains intact while the deepest hole is etched to completion. Once all holes have landed on the etch stop, a further etch selective to the insulator material is carried out to punch through the etch stop and expose underlying wordlines. Contacts are deposited into the holes.