公开(公告)号：US20170293332A1

公开(公告)日：2017-10-12

申请号：US15093042

申请日：2016-04-07

Applicant: Intel Corporation

Inventor： EFRAIM ROTEM ,  TOD F. SCHIFF ,  DORON RAJWAN ,  JEFFREY M. JULL ,  JAMES G. HERMERDING, II ,  NIR ROSENZWEIG ,  MAYTAL TOLEDANO ,  ALEXANDER B. UAN-ZO-LI

IPC: G06F1/26 ,  G08B21/18

Abstract: One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.

公开(公告)号：US20170092996A1

公开(公告)日：2017-03-30

申请号：US14866870

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： JORGE P. RODRIGUEZ ,  ALEXANDER B. UAN-ZO-LI ,  NAOKI MATSUMURA ,  ANDY KEATES ,  JAMES G. HERMERDING, II

IPC: H01M10/48 ,  H02J1/14 ,  G05B15/02

Abstract: Various embodiments may be generally directed to techniques for using an observed battery stress history to manage operation of a computing system component in a high power performance mode when powered by a battery. Various embodiments include techniques for tracking stresses to a battery. Various embodiments include techniques for comparing the battery stress history to a degradation baseline for the battery. Various embodiments include techniques for developing a degradation baseline for a battery including, for example, a degradation baseline based on expected stress to a battery and/or a degradation baseline based on a battery reliability model. Various embodiments include techniques for determining a battery stress surplus or deficit. Various embodiments include techniques for managing operation of a performance enhancing mode or high power performance mode of a computing system component based on the determined battery stress surplus or deficit.

公开(公告)号：US20170351322A1

公开(公告)日：2017-12-07

申请号：US15402114

申请日：2017-01-09

Applicant: INTEL CORPORATION

Inventor： ALEXANDER B. UAN-ZO-LI ,  JORGE P. RODRIGUEZ ,  PHILIP R. LEHWALDER ,  PATRICK K. LEUNG ,  JAMES G. HERMERDING, II ,  VASUDEVAN SRINIVASAN

IPC: G06F1/32 ,  G06F1/28

CPC classification number: G06F1/3296 ,  G06F1/28 ,  G06F1/3212 ,  Y02D10/172 ,  Y02D10/174

Abstract: An apparatus may include first circuitry coupled to one or more platform components, the first circuitry operative to receive an unfiltered input voltage signal, compare a first voltage level of the unfiltered input voltage signal to a first reference voltage level, and generate a control signal operative to lower operation power of one or more of the one or more platform components when the first voltage level is less than the first reference voltage level.