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    COALESCING ADJACENT GATHER/SCATTER OPERATIONS
    1.
    发明申请
    COALESCING ADJACENT GATHER/SCATTER OPERATIONS 有权

    公开(公告)号：US20230137812A1

    公开(公告)日：2023-05-04

    申请号：US18092298

    申请日：2022-12-31

    Applicant: Intel Corporation

    Inventor： Andrew T. FORSYTH ,  Brian J. HICKMANN ,  Jonathan C. HALL ,  Christopher J. HUGHES

    IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/80 ,  G06F13/42

    Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

    MEMORY FAULT SUPPRESSION VIA RE-EXECUTION AND HARDWARE FSM
    5.
    发明申请
    MEMORY FAULT SUPPRESSION VIA RE-EXECUTION AND HARDWARE FSM 有权
    通过重新执行和硬件FSM的内存故障抑制

    公开(公告)号：US20160179632A1

    公开(公告)日：2016-06-23

    申请号：US14581859

    申请日：2014-12-23

    Applicant: INTEL CORPORATION

    Inventor： Ramon MATAS ,  Roger GRAMUNT ,  Chung-Lun CHAN ,  Benjamin C. CHAFFIN ,  Aditya KESIRAJU ,  Jonathan C. HALL ,  Jesus CORBAL

    IPC: G06F11/14

    CPC classification number: G06F11/141 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/38 ,  G06F9/3859 ,  G06F9/3865

    Abstract: Exemplary aspects are directed toward resolving fault suppression in hardware, which at the same time does not incur a performance hit. For example, when multiple instructions are executing simultaneously, a mask can specify which elements need not be executed. If the mask is disabled, those elements do not need to be executed. A determination is then made as to whether a fault happens in one of the elements that have been disabled. If there is a fault in one of the elements that has been disabled, a state machine re-fetches the instructions in a special mode. More specifically, the state machine determines if the fault is on a disabled element, and if the fault is on a disabled element, then the state machine specifies that the fault should be ignored. If during the first execution there was no mask, if there is an error present during execution, then the element is re-run with the mask to see if the error is a “real” fault.

    Abstract translation: 示例性方面涉及解决在硬件中的故障抑制，其同时不会导致性能下降。 例如，当多个指令同时执行时，掩码可以指定不需要执行哪些元素。 如果禁用掩码，则不需要执行这些元素。 然后确定在已经被禁用的元素之一中是否发生故障。 如果其中一个元素中存在故障，则状态机将以特殊模式重新读取指令。 更具体地说，状态机确定故障是否在禁用元件上，如果故障位于禁用元件上，则状态机指定故障应被忽略。 如果在第一次执行期间没有掩码，如果在执行期间存在错误，则使用掩码重新运行该元素，以查看错误是否为“真实”错误。

    COALESCING ADJACENT GATHER/SCATTER OPERATIONS
    6.
    发明申请
    COALESCING ADJACENT GATHER/SCATTER OPERATIONS 审中-公开
    加油相机/散热器操作

    公开(公告)号：US20160103787A1

    公开(公告)日：2016-04-14

    申请号：US14975292

    申请日：2015-12-18

    Applicant: Intel Corporation

    Inventor： Andrew T. FORSYTH ,  Brian J. HICKMANN ,  Jonathan C. HALL ,  Christopher J. HUGHES

    IPC: G06F15/80 ,  G06F12/08 ,  G06F9/30

    CPC classification number: G06F9/3853 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

    Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

    Abstract translation: 根据一个实施例，处理器包括指令解码器，用于解码从存储器收集数据元素的第一指令，所述第一指令具有指定第一存储位置的第一操作数和指定存储多个数据元素的第一存储器地址的第二操作数 。 处理器还包括执行单元，其响应于第一指令而耦合到指令解码器，基于由第二操作数指示的第一存储器地址从存储器位置读取连续的第一和第二数据元素，并且 将所述第一数据元素存储在所述第一存储位置的第一条目中，以及将第二数据元素存储在与所述第一存储位置的所述第一条目相对应的第二存储位置的第二条目中。

    COALESCING ADJACENT GATHER/SCATTER OPERATIONS
    7.
    发明申请
    COALESCING ADJACENT GATHER/SCATTER OPERATIONS 有权

    公开(公告)号：US20210406026A1

    公开(公告)日：2021-12-30

    申请号：US17316680

    申请日：2021-05-10

    Applicant: Intel Corporation

    Inventor： Andrew T. FORSYTH ,  Brian J. HICKMANN ,  Jonathan C. HALL ,  Christopher J. HUGHES

    IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/80 ,  G06F13/42

    Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

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