公开(公告)号：US20210117535A1

公开(公告)日：2021-04-22

申请号：US17114246

申请日：2020-12-07

Applicant: INTEL CORPORATION

Inventor： Michael LEMAY ,  David M. DURHAM ,  Michael E. KOUNAVIS ,  Barry E. HUNTLEY ,  Vedvyas SHANBHOGUE ,  Jason W. BRANDT ,  Josh TRIPLETT ,  Gilbert NEIGER ,  Karanvir GREWAL ,  Baiju PATEL ,  Ye ZHUANG ,  Jr-Shian TSAI ,  Vadim SUKHOMLINOV ,  Ravi SAHITA ,  Mingwei ZHANG ,  James C. FARWELL ,  Amitabh DAS ,  Krishna BHUYAN

IPC: G06F21/53 ,  G06F12/02

Abstract: Disclosed embodiments relate to encoded inline capabilities. In one example, a system includes a trusted execution environment (TEE) to partition an address space within a memory into a plurality of compartments each associated with code to execute a function, the TEE further to assign a message object in a heap to each compartment, receive a request from a first compartment to send a message block to a specified destination compartment, respond to the request by authenticating the request, generating a corresponding encoded capability, conveying the encoded capability to the destination compartment, and scheduling the destination compartment to respond to the request, and subsequently, respond to a check capability request from the destination compartment by checking the encoded capability and, when the check passes, providing a memory address to access the message block, and, otherwise, generating a fault, wherein each compartment is isolated from other compartments.

公开(公告)号：US20200004953A1

公开(公告)日：2020-01-02

申请号：US16024547

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Michael LEMAY ,  David M. DURHAM ,  Michael E. KOUNAVIS ,  Barry E. HUNTLEY ,  Vedvyas SHANBHOGUE ,  Jason W. BRANDT ,  Josh TRIPLETT ,  Gilbert NEIGER ,  Karanvir GREWAL ,  Baiju V. PATEL ,  Ye ZHUANG ,  Jr-Shian TSAI ,  Vadim SUKHOMLINOV ,  Ravi SAHITA ,  Mingwei ZHANG ,  James C. FARWELL ,  Amitabh DAS ,  Krishna BHUYAN

IPC: G06F21/53 ,  G06F12/02

Abstract: Disclosed embodiments relate to encoded inline capabilities. In one example, a system includes a trusted execution environment (TEE) to partition an address space within a memory into a plurality of compartments each associated with code to execute a function, the TEE further to assign a message object in a heap to each compartment, receive a request from a first compartment to send a message block to a specified destination compartment, respond to the request by authenticating the request, generating a corresponding encoded capability, conveying the encoded capability to the destination compartment, and scheduling the destination compartment to respond to the request, and subsequently, respond to a check capability request from the destination compartment by checking the encoded capability and, when the check passes, providing a memory address to access the message block, and, otherwise, generating a fault, wherein each compartment is isolated from other compartments.

公开(公告)号：US20230176934A1

公开(公告)日：2023-06-08

申请号：US18090373

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Robert SOULE ,  Rajit MANOHAR ,  Jr-Shian TSAI ,  Edmund CHEN ,  Uri V. CUMMINGS ,  Pietro BRESSANA ,  Rui LI

IPC: G06F9/54

CPC classification number: G06F9/547 ,  G06F9/544

Abstract: Examples described herein relate to a network interface device that includes packet processing circuitry and circuitry. In some examples, the circuitry is to execute a first process to provide a remote procedure call (RPC) interface for a second process. In some examples, the second process comprises a business logic. In some examples, resource and deployment definitions of the first and second processes are based on an Interface Description Language (IDL) and a memory allocation. In some examples, the memory allocation among the processes provides share at least one RPC message as at least one formatted object accessible from memory.

公开(公告)号：US20230161652A1

公开(公告)日：2023-05-25

申请号：US18090356

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Robert SOULE ,  Rajit MANOHAR ,  Jr-Shian TSAI ,  Edmund CHEN ,  Uri V. CUMMINGS ,  Pietro BRESSANA ,  Rui LI

IPC: G06F9/54

CPC classification number: G06F9/547 ,  G06F9/544

Abstract: Examples described herein relate to a network interface device that includes packet processing circuitry and circuitry. In some examples, the circuitry is to execute a first process of partitioned processes to provide a remote procedure call (RPC) interface for a second process. In some examples, the second process of the partitioned processes includes a business logic. In some examples, the partitioned processes comprise resource and deployment definition are based on an Interface Description Language (IDL) and a memory allocation.

公开(公告)号：US20210099398A1

公开(公告)日：2021-04-01

申请号：US17067564

申请日：2020-10-09

Applicant: Intel Corporation

Inventor： Ren WANG ,  Tsung-Yuan C. TAI ,  Jr-Shian TSAI

IPC: H04L12/911 ,  H04L12/925 ,  H04N1/333 ,  H04L1/18 ,  H04L12/835 ,  H04L12/12 ,  H04L29/08

Abstract: In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request that at least one network node generate, at least in part, information. The information may be to permit selection, at least in part, of (1) at least one power consumption state of the at least one network node, and (2) at least one time period. The at least one time period may be to elapse, after receipt by at least one other network node of at least one packet, prior to requesting at least one change in the at least one power consumption state. The at least one packet may be to be transmitted to the at least one network node. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.

公开(公告)号：US20240192981A1

公开(公告)日：2024-06-13

申请号：US18285212

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Wei WANG ,  Kun TIAN ,  Gilbert NEIGER ,  Rajesh SANKARAN ,  Asit MALLICK ,  Jr-Shian TSAI ,  Jacob Jun PAN ,  Mesut ERGIN

IPC: G06F9/455 ,  G06F9/30

CPC classification number: G06F9/45558 ,  G06F9/30145 ,  G06F2009/45579

Abstract: Embodiments of exitless guest to host (G2H) notification are described. In some embodiments, G2H is provided via an instruction. An exemplary processor includes decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode; and execution processing resources to execute the decoded single instruction according to the at least the opcode to cause an exitless guest to host notification from a virtual processor to a physical or virtual processor.

公开(公告)号：US20220150055A1

公开(公告)日：2022-05-12

申请号：US17437342

申请日：2019-04-19

Applicant: Intel Corporation

Inventor： Bo CUI ,  Cunming LIANG ,  Jr-Shian TSAI ,  Ping YU ,  Xiaobing QIAN ,  Xuekun HU ,  Lin LUO ,  Shravan NAGRAJ ,  Xiaowen ZHANG ,  Mesut A. ERGIN ,  Tsung-Yuan C. TAI ,  Andrew J. HERDRICH

IPC: H04L9/08 ,  H04L9/06 ,  H04L9/40

Abstract: In some examples, for process-to-process communication, such as in function linking, a virtual channel can be provisioned to provide virtual machine to virtual machine communications. In response to a transmit request from a source virtual machine, the virtual channel can cause a data copy from a source buffer associated with the source virtual machine without decryption or encryption. The virtual channel provisions a key identifier for the copied data. The destination virtual machine can receive an indication data is available and can cause the data to be decrypted using a key accessed using the key identifier and source address of the copied data. In addition, the data can be encrypted using a second, different key for storage in a destination buffer associated with the destination virtual machine. In some examples, the key identifier and source address is managed by the virtual channel and is not visible to virtual machine or hypervisor.

公开(公告)号：US20220114270A1

公开(公告)日：2022-04-14

申请号：US17560193

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Ren WANG ,  Sameh GOBRIEL ,  Somnath PAUL ,  Yipeng WANG ,  Priya AUTEE ,  Abhirupa LAYEK ,  Shaman NARAYANA ,  Edwin VERPLANKE ,  Mrittika GANGULI ,  Jr-Shian TSAI ,  Anton SOROKIN ,  Suvadeep BANERJEE ,  Abhijit DAVARE ,  Desmond KIRKPATRICK

IPC: G06F21/62

Abstract: Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.

公开(公告)号：US20200097269A1

公开(公告)日：2020-03-26

申请号：US16142401

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Yipeng WANG ,  Ren WANG ,  Tsung-Yuan C. TAI ,  Jr-Shian TSAI ,  Xiangyang GUO

IPC: G06F8/41 ,  G06F9/455

Abstract: Examples may include a method of compiling a declarative language program for a virtual switch. The method includes parsing the declarative language program, the program defining a plurality of match-action tables (MATs), translating the plurality of MATs into intermediate code, and parsing a core identifier (ID) assigned to each one of the plurality of MATs. When the core IDs of the plurality of MATs are the same, the method includes connecting intermediate code of the plurality of MATs using function calls, and translating the intermediate code of the plurality of MATs into machine code to be executed by a core identified by the core IDs.