中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.015 seconds)

    APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR USAGE RESTRICTIONS CRYPTOGRAPHICALLY TIED WITH DATA
    1.
    发明申请
    APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR USAGE RESTRICTIONS CRYPTOGRAPHICALLY TIED WITH DATA 有权

    公开(公告)号：US20210203504A1

    公开(公告)日：2021-07-01

    申请号：US16729352

    申请日：2019-12-28

    Applicant: Intel Corporation

    Inventor： Jason W. BRANDT

    IPC: H04L9/32 ,  G06F9/30 ,  H04L9/08

    Abstract: Systems, methods, and apparatuses relating to circuitry to implement an instruction to create and/or use data that is restricted in how it can be used are described. In one embodiment, a hardware processor comprises a decoder of a core to decode a single instruction into a decoded single instruction, the single instruction comprising a first input operand of a handle including a ciphertext of an encryption key (e.g., cryptographic key), an authentication tag, and additional authentication data, and a second input operand of data encrypted with the encryption key, and an execution unit of the core to execute the decoded single instruction to: perform a first check of the authentication tag against the ciphertext and the additional authentication data for any modification to the ciphertext or the additional authentication data, perform a second check of a current request of the core against one or more restrictions specified by the additional authentication data of the handle, decrypt the ciphertext to generate the encryption key only when the first check indicates no modification to the ciphertext or the additional authentication data, and the second check indicates the one or more restrictions are not violated, decrypt the data encrypted with the encryption key to generate unencrypted data, and provide the unencrypted data as a resultant of the single instruction.

    METHOD AND APPARATUS FOR PROCESSOR TRACE TRIGGER TRACING
    3.
    发明申请
    METHOD AND APPARATUS FOR PROCESSOR TRACE TRIGGER TRACING 有权

    公开(公告)号：US20250004871A1

    公开(公告)日：2025-01-02

    申请号：US18217501

    申请日：2023-06-30

    Applicant: Intel Corporation

    Inventor： Beeman STRONG ,  Stanislav BRATANOV ,  Markus METZGER ,  Jason W. BRANDT ,  Stalinselvaraj JEYASINGH

    IPC: G06F11/07

    Abstract: Apparatus and method for a processor trace trigger tracing. A processor, comprising: a plurality of processing cores configurable as a plurality of logical processors; processor trace circuitry to perform trace operations to capture and process information related to program code executed by one or more of the logical processors; a debug unit to perform debug operations and collect debug data related to execution of the program code; a performance monitoring unit (PMU) comprising a plurality of counter registers, the PMU to collect performance data related to execution of the program code; and a plurality of trigger units, each trigger unit associated with a logical processor of the plurality of logical processors and configured to communicate trigger event data to the processor trace circuitry in response to trigger events received from at least one of the debug unit and the PMU in accordance with values of configuration bits in a corresponding trigger unit configuration register.

    APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR USAGE RESTRICTIONS CRYPTOGRAPHICALLY TIED WITH DATA
    6.
    发明公开
    APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR USAGE RESTRICTIONS CRYPTOGRAPHICALLY TIED WITH DATA 审中-公开

    公开(公告)号：US20240250823A1

    公开(公告)日：2024-07-25

    申请号：US18589125

    申请日：2024-02-27

    Applicant: Intel Corporation

    Inventor： Jason W. BRANDT

    IPC: H04L9/32 ,  G06F9/30 ,  H04L9/08

    CPC classification number: H04L9/3226 ,  G06F9/30178 ,  H04L9/0861 ,  H04L2209/12

    Abstract: Systems, methods, and apparatuses relating to circuitry to implement an instruction to create and/or use data that is restricted in how it can be used are described. In one embodiment, a hardware processor comprises a decoder of a core to decode a single instruction into a decoded single instruction, the single instruction comprising a first input operand of a handle including a ciphertext of an encryption key (e.g., cryptographic key), an authentication tag, and additional authentication data, and a second input operand of data encrypted with the encryption key, and an execution unit of the core to execute the decoded single instruction to: perform a first check of the authentication tag against the ciphertext and the additional authentication data for any modification to the ciphertext or the additional authentication data, perform a second check of a current request of the core against one or more restrictions specified by the additional authentication data of the handle, decrypt the ciphertext to generate the encryption key only when the first check indicates no modification to the ciphertext or the additional authentication data, and the second check indicates the one or more restrictions are not violated, decrypt the data encrypted with the encryption key to generate unencrypted data, and provide the unencrypted data as a resultant of the single instruction.

    CREATING, USING, AND MANAGING PROTECTED CRYPTOGRAPHY KEYS
    8.
    发明公开
    CREATING, USING, AND MANAGING PROTECTED CRYPTOGRAPHY KEYS 审中-公开

    公开(公告)号：US20230269076A1

    公开(公告)日：2023-08-24

    申请号：US18040245

    申请日：2021-08-27

    Applicant: Intel Corporation

    Inventor： Jason W. BRANDT ,  Steven L. GROBMAN ,  Vedvyas SHANBHOGUE

    IPC: H04L9/08 ,  H04L9/32

    CPC classification number: H04L9/0822 ,  H04L9/32

    Abstract: System, method, and apparatus embodiments for creating, using, and managing protected cryptography keys are described. In an embodiment, an apparatus includes a decoder, an execution unit, and a cache. The decoder is to decode a single instruction into a decoded single instruction, the single instruction having a first source operand to specify encrypted data and a second source operand to specify a handle including a first including ciphertext of an encryption key, an integrity tag, and additional authentication data. The execution unit is to execute the decoded single instruction to perform a first check of the integrity tag against the ciphertext and the additional authentication data for any modification to the ciphertext or the additional authentication data, perform a second check of a current request against one or more restrictions specified by the additional authentication data of the handle, decrypt the ciphertext to generate an encryption key only when the first check indicates no modification to the ciphertext or the additional authentication data and the second check indicates the one or more restrictions are not violated, decrypt the encrypted data with the encryption key to generate unencrypted data, and provide the unencrypted data as a result of the single instruction. The cache is to store the handle, wherein only a portion of the integrity tag is to be used in a lookup of the handle.

Patent Agency Ranking