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公开(公告)号：US10922166B2
公开(公告)日：2021-02-16
申请号：US16366958
申请日：2019-03-27
Applicant: Intel Corporation
Inventor： Justin Hogaboam
Abstract: Apparatus and method including a probabilistic compute element for analyzing measured quantum values and responsively adjusting error correction parameters. For example, one embodiment of an apparatus comprises: a quantum controller to generate physical pulses directed to qubits on a quantum processor in response to operations specified in a quantum runtime; quantum measurement circuitry to measure quantum values associated with the qubits following completion of at least a first cycle of quantum runtime operations; and a probabilistic compute engine to analyze the one or more quantum values using inferencing and to responsively adjust a quantum error correction depth value for minimizing a number of errors to be detected on subsequent cycles of the quantum runtime.
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公开(公告)号：US11526793B2
公开(公告)日：2022-12-13
申请号：US16152311
申请日：2018-10-04
Applicant: INTEL CORPORATION
Inventor： Sahar Daraeizadeh , Anne Matsuura , Justin Hogaboam
IPC: G06N10/00 , G06T15/00 , G06N7/00 , G06F30/3308
Abstract: Apparatus and method for a full quantum state simulation. A quantum state simulation system may include a simulation configurator to map quantum register state data of a quantum processor at a first time to a representational data structure and generate a first quantum state image based on the representational data structure. The quantum state simulation system may also include a quantum state simulator to simulate the quantum register state data at a second time using the quantum register state data in the first quantum state image to update a second quantum state image, and store the first and second quantum state images to a data store.
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3.发明授权公开(公告)号：US11374594B2
公开(公告)日：2022-06-28
申请号：US15972114
申请日：2018-05-05
Applicant: Intel Corporation
Inventor： Justin Hogaboam , Narayan Srinivasa
Abstract: Apparatus and method for neural network learning to detect and correct quantum errors. For example, one embodiment of an apparatus comprises. For example, one embodiment of an apparatus comprises: a quantum processor comprising one or more data quantum bits (qbits) and one or more ancilla qbits; an error decoder to decode a state of at least one of the ancilla qbits to generate an error syndrome related to one or more qbit errors; a neural network to evaluate the error syndrome and to either identify a known corrective response for correcting the error or to perform unsupervised learning to identify a corrective response to the error syndrome.
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公开(公告)号：US11704588B2
公开(公告)日：2023-07-18
申请号：US16144963
申请日：2018-09-27
Applicant: Intel Corporation
Inventor： Xiang Zou , Justin Hogaboam
CPC classification number: G06N10/70 , G06F9/22 , G06F9/3017 , G06F9/30101 , G06F9/3877
Abstract: Apparatus and method for injected spin echo sequences in a quantum processor. For example, one embodiment of a processor includes a decoder to decode quantum instructions to generate quantum microoperations (uops) and to decode non-quantum instructions to generate non-quantum uops, execution circuitry to execute the quantum uops and non-quantum uops, and a corrective sequence data structure to identify and/or store corrective sets of uops for one or more of the quantum instructions. The decoder is to query the corrective sequence data structure upon receiving a first quantum instruction to determine if one or more corrective uops exist, and if the one or more corrective uops exist, the decoder is to submit the one or more corrective uops for execution by the execution circuitry.
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5.发明授权公开(公告)号：US11513552B2
公开(公告)日：2022-11-29
申请号：US16231100
申请日：2018-12-21
Applicant: Intel Corporation
Inventor： Justin Hogaboam , Sonika Johri , Anne Matsuura
Abstract: Apparatus and method for dynamically adjusting a quantum computer clock frequency. For example, one embodiment of an apparatus comprises: a quantum execution unit to execute quantum operations specified by a quantum runtime; a qubit drive controller to translate the quantum operations into physical pulses directed to qubits on a quantum chip at a first cycle frequency; a spin echo sequencer to issue spin echo command sequences to cause the qubit drive controller to generate a sequence of spin echo pulses at the first cycle frequency; and qubit measurement circuitry to measure the qubits and to store qubit timing data for each qubit, the qubit timing data indicating a coherence time or an amount of computational time available for each qubit to perform quantum operations.
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Patent Agency Ranking
公开(公告)号：US11308248B2
公开(公告)日：2022-04-19
申请号：US15972119
申请日：2018-05-05
Applicant: Intel Corporation
Inventor： Anne Matsuura , Sonika Johri , Justin Hogaboam
Abstract: Apparatus and method for a full quantum system simulator. For example, one embodiment of a method comprises: initializing a quantum computing system simulator for simulating multiple layers of a quantum system including one or more non-quantum layers and one or more physical quantum device layers of the quantum system; simulating a first set of operations of the one or more non-quantum layers of the quantum system to generate first simulation results; simulating a second set of operations of the one or more quantum device layers of the quantum system to generate second simulation results; analyzing the first and second simulation results to provide at least one configuration recommendation for the quantum system.
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公开(公告)号：US12039234B2
公开(公告)日：2024-07-16
申请号：US17723217
申请日：2022-04-18
Applicant: Intel Corporation
Inventor： Anne Matsuura , Sonika Johri , Justin Hogaboam
Abstract: Apparatus and method for a full quantum system simulator. For example, one embodiment of a method comprises: initializing a quantum computing system simulator for simulating multiple layers of a quantum system including one or more non-quantum layers and one or more physical quantum device layers of the quantum system; simulating a first set of operations of the one or more non-quantum layers of the quantum system to generate first simulation results; simulating a second set of operations of the one or more quantum device layers of the quantum system to generate second simulation results; analyzing the first and second simulation results to provide at least one configuration recommendation for the quantum system.
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公开(公告)号：US11954563B2
公开(公告)日：2024-04-09
申请号：US17546974
申请日：2021-12-09
Applicant: Intel Corporation
Inventor： Nicolas Sawaya , Anne Matsuura , Justin Hogaboam
Abstract: Apparatus and method for error reduction in distributed quantum computing via fusing-and-decomposing gates. For example, one embodiment of an apparatus comprises: a quantum module comprising a plurality of qubits; unitary generation logic to combine a group of quantum gates to form at least one unitary operation; decomposition logic to decompose the unitary operation into multiple alternative gate sequences comprising either exact gate sequences or approximate gate sequences; and selection logic to evaluate the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.
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9.发明授权公开(公告)号：US11748649B2
公开(公告)日：2023-09-05
申请号：US16714644
申请日：2019-12-13
Applicant: Intel Corporation
Inventor： Xiang Zou , Justin Hogaboam , Adam Holmes , Sonika Johri
Abstract: Apparatus and method for specifying quantum operation parallelism. For example, one embodiment of an apparatus comprises: instruction fetch circuitry to fetch a plurality of quantum instructions from a memory or a cache; slice-based instruction processing circuitry to identify quantum circuit slices comprising sets of one or more of the plurality of quantum instructions; and one or more instruction decoders to decode the quantum instructions to generate quantum microoperations; and quantum execution circuitry to execute sets of the quantum microoperations in parallel based on the quantum circuit slices.
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10.发明公开公开(公告)号：US20230186139A1
公开(公告)日：2023-06-15
申请号：US17546974
申请日：2021-12-09
Applicant: Intel Corporation
Inventor： Nicolas Sawaya , Anne Matsuura , Justin Hogaboam
Abstract: Apparatus and method for error reduction in distributed quantum computing via fusing-and-decomposing gates. For example, one embodiment of an apparatus comprises: a quantum module comprising a plurality of qubits; unitary generation logic to combine a group of quantum gates to form at least one unitary operation; decomposition logic to decompose the unitary operation into multiple alternative gate sequences comprising either exact gate sequences or approximate gate sequences; and selection logic to evaluate the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.
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