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公开(公告)号：US11907808B2
公开(公告)日：2024-02-20
申请号：US17464583
申请日：2021-09-01
Applicant: Intel Corporation
Inventor： Albert Schmitz , Anne Matsuura , Ravi Pillarisetty , Shavindra Premaratne , Justin Hogaboam , Lester Lampert
Abstract: Apparatus and method for measurement-free (MF) quantum error correction (QEC). For example, one embodiment of a method comprises: determining an error syndrome on a first subset of ancilla qubits of a quantum processor; decoding the error syndrome to produce decoded results on a second subset of ancilla qubits of the quantum processor; applying the decoded results to one or more system qubits; and unconditionally resetting the first subset and/or second subset of ancilla qubits to remove entropy and/or noise from the quantum system, wherein the operations of determining the error syndrome, decoding the error syndrome, applying the error syndrome, and unconditionally resetting the first and/or second subset of ancilla qubits are performed responsive to a qubit controller executing quantum control instructions provided from or derived from a script and without transmitting measurement data related to the error syndrome to a non-quantum computing device.
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公开(公告)号：US11526793B2
公开(公告)日：2022-12-13
申请号：US16152311
申请日：2018-10-04
Applicant: INTEL CORPORATION
Inventor： Sahar Daraeizadeh , Anne Matsuura , Justin Hogaboam
IPC: G06N10/00 , G06T15/00 , G06N7/00 , G06F30/3308
Abstract: Apparatus and method for a full quantum state simulation. A quantum state simulation system may include a simulation configurator to map quantum register state data of a quantum processor at a first time to a representational data structure and generate a first quantum state image based on the representational data structure. The quantum state simulation system may also include a quantum state simulator to simulate the quantum register state data at a second time using the quantum register state data in the first quantum state image to update a second quantum state image, and store the first and second quantum state images to a data store.
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公开(公告)号：US12039234B2
公开(公告)日：2024-07-16
申请号：US17723217
申请日：2022-04-18
Applicant: Intel Corporation
Inventor： Anne Matsuura , Sonika Johri , Justin Hogaboam
Abstract: Apparatus and method for a full quantum system simulator. For example, one embodiment of a method comprises: initializing a quantum computing system simulator for simulating multiple layers of a quantum system including one or more non-quantum layers and one or more physical quantum device layers of the quantum system; simulating a first set of operations of the one or more non-quantum layers of the quantum system to generate first simulation results; simulating a second set of operations of the one or more quantum device layers of the quantum system to generate second simulation results; analyzing the first and second simulation results to provide at least one configuration recommendation for the quantum system.
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公开(公告)号：US11954563B2
公开(公告)日：2024-04-09
申请号：US17546974
申请日：2021-12-09
Applicant: Intel Corporation
Inventor： Nicolas Sawaya , Anne Matsuura , Justin Hogaboam
Abstract: Apparatus and method for error reduction in distributed quantum computing via fusing-and-decomposing gates. For example, one embodiment of an apparatus comprises: a quantum module comprising a plurality of qubits; unitary generation logic to combine a group of quantum gates to form at least one unitary operation; decomposition logic to decompose the unitary operation into multiple alternative gate sequences comprising either exact gate sequences or approximate gate sequences; and selection logic to evaluate the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.
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5.发明公开公开(公告)号：US20230186139A1
公开(公告)日：2023-06-15
申请号：US17546974
申请日：2021-12-09
Applicant: Intel Corporation
Inventor： Nicolas Sawaya , Anne Matsuura , Justin Hogaboam
Abstract: Apparatus and method for error reduction in distributed quantum computing via fusing-and-decomposing gates. For example, one embodiment of an apparatus comprises: a quantum module comprising a plurality of qubits; unitary generation logic to combine a group of quantum gates to form at least one unitary operation; decomposition logic to decompose the unitary operation into multiple alternative gate sequences comprising either exact gate sequences or approximate gate sequences; and selection logic to evaluate the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.
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Patent Agency Ranking
公开(公告)号：US20240104413A1
公开(公告)日：2024-03-28
申请号：US17954131
申请日：2022-09-27
Applicant: Intel Corporation
Inventor： Todor Mladenov , Sahar Daraeizadeh , Anne Matsuura
IPC: G06N10/20
CPC classification number: G06N10/20
Abstract: Technologies for a hybrid digital/analog processor for a quantum computer are disclosed. In the illustrative embodiment, a hybrid digital/analog processor may be able to process digital instructions as well as analog instructions. The digital instructions may be, e.g., read from or write to memory or registers, perform an arithmetic operation, perform a branch, etc. The analog instructions may be to, e.g., provide an analog voltage to a particular electrode of a qubit, provide an analog pulse to a qubit, measure a reflection of an analog signal from a qubit, etc. The integration of analog operations in the hybrid digital/analog processor can improve performance by, e.g., lowering latency and lowering power usage.
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公开(公告)号：US11550977B2
公开(公告)日：2023-01-10
申请号：US16261113
申请日：2019-01-29
Applicant: Intel Corporation
Inventor： Sahar Daraeizadeh , Anne Matsuura , Xiang Zou , Sonika Johri
Abstract: Apparatus and method for replacing portions of a quantum circuit with multi-qubit gates. For example, one embodiment of an apparatus comprises: a quantum circuit analyzer to evaluate an original quantum circuit specification including one or more sub-circuits of the original quantum circuit specification, the quantum circuit analyzer to generate results of the evaluation; a quantum circuit generator to generate a new quantum circuit specification based on the results of the evaluation generated by the quantum circuit analyzer, the quantum circuit generator to generate the new quantum circuit specification by, at least in part, replacing the one or more sub-circuits of the original quantum circuit specification with one or more multi-qubit gates.
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公开(公告)号：US20210182723A1
公开(公告)日：2021-06-17
申请号：US16714267
申请日：2019-12-13
Applicant: Intel Corporation
Inventor： Albert Schmitz , Sonika Johri , Anne Matsuura
Abstract: Apparatus and method for hardware-specific quantum circuit synthesis. For example, one embodiment of an apparatus comprises: one or more memory and/or storage devices to store quantum computation specifications and hardware-specific constraints associated with a quantum processor; and a quantum circuit synthesizer to generate a hardware-optimal quantum circuit based on the quantum computation specifications and the hardware-specific constraints.
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公开(公告)号：US20250021849A1
公开(公告)日：2025-01-16
申请号：US18220212
申请日：2023-07-10
Applicant: Intel Corporation
Inventor： Sahar Daraeizadeh , Todor Mladenov , Xiang Zou , Anne Matsuura
IPC: G06N10/20
Abstract: Apparatus and method for a quantum control processor. For example, one embodiment of a QCP comprises: instruction fetch logic to fetch instructions from a memory, the instructions including quantum instructions; decode logic to decode the quantum instructions into a first plurality of quantum microoperations; translation logic translate the first plurality of quantum microoperations into a second plurality of quantum microoperations based on characteristics of a plurality of quantum controller cores coupled to the quantum control processor; and issue logic to synchronously issue the second plurality of quantum microoperations in parallel to the plurality of quantum controller cores.
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10.发明授权公开(公告)号：US11513552B2
公开(公告)日：2022-11-29
申请号：US16231100
申请日：2018-12-21
Applicant: Intel Corporation
Inventor： Justin Hogaboam , Sonika Johri , Anne Matsuura
Abstract: Apparatus and method for dynamically adjusting a quantum computer clock frequency. For example, one embodiment of an apparatus comprises: a quantum execution unit to execute quantum operations specified by a quantum runtime; a qubit drive controller to translate the quantum operations into physical pulses directed to qubits on a quantum chip at a first cycle frequency; a spin echo sequencer to issue spin echo command sequences to cause the qubit drive controller to generate a sequence of spin echo pulses at the first cycle frequency; and qubit measurement circuitry to measure the qubits and to store qubit timing data for each qubit, the qubit timing data indicating a coherence time or an amount of computational time available for each qubit to perform quantum operations.
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